Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2002-07-23
2004-06-29
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S119000, C327S156000
Reexamination Certificate
active
06756821
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
This invention relates generally to signal processing and more particularly to logic gates.
2. Description of Related Art
Digital logic circuits such as AND gates, NAND gates, NOR gates, OR gates, exclusive OR gates, latches, inverters, flip-flops, et cetera are known to be used in a wide variety of electronic devices. For instance, digital logic circuits are used in all types of computers (e.g., laptops, personal computers, personal digital assistants, et cetera), entertainment equipment (e.g., receivers, televisions, et cetera), and wireless communication devices (e.g., cellular telephones, radios, wireless local area network devices, et cetera).
Typically, digital logic circuits are part of a larger circuit, which is fabricated on an integrated circuit. For example, a local oscillator within a radio frequency (RF) transmitter and/or receiver includes a plurality of flip-flops and logic gates in its divider feedback circuit to provide adjustable divider values. As is known, by adjusting the divider value in a local oscillator, the resulting local oscillation can be adjusted to desired values.
Within the feedback divider circuit, the logic gates are included to achieve divider values different than powers of 2. Issues arise with the use of traditional logic gates in applications that push the operating limits of an integrated circuit process. For example, for a multi-gigahertz frequency range of operation, traditional logic gates create a bottleneck for the local oscillator due to the time it takes for each logic gate to complete its function.
Another related issue results as supply voltages decrease for newer integrated circuit fabrication processes (e.g., CMOS, gallium arsenide, silicon germanium, et cetera). As the supply voltage decreases, the available voltage to enable stacked transistors within the logic gates decreases. As such, the transistors have slower rise and fall times than if more voltage were available. Accordingly, it takes longer for the logic gate to complete its function due to the slower rise and fall times.
One obvious solution for increasing the rise and fall times of logic gates is to increase the supply voltage. However, by increasing the supply voltage, power consumption increases, arid, in many ways, defeats the benefit of newer integrated circuit fabrication processes.
Further, in high performance applications, such as a radio frequency integrated circuit, differential signaling is used to improve noise immunity. Accordingly, the logic gates within the divider circuit of the local oscillator are differential circuits. As is known, an AND function and an OR function are achieved by the same combination of stack transistors by switching the plurality of the inputs, The number of transistors in each stack is dependent on the number of inputs. For example, a 2 input AND gate or OR gate function has 2 sets of 2 transistor stacked on a current source, a 3 input AND gate or OR gate function has 2 sets of 3 transistor stacks, et cetera. As such, differential logic gates suffer from the above-mentioned issues as well.
Therefore, a need exists for a high-speed differential logic gate that operates effectively in the multi-gigahertz range and is power consumption efficient.
BRIEF SUMMARY OF THE INVENTION
The high-speed differential signaling logic gate of the present invention substantially meets these needs and others. In one embodiment of a high speed differential signaling logic gate, it includes a 1
st
input transistor, 2
nd
input transistor, complimentary transistor, current source, a 1
st
load, and a 2
nd
load. The 1
st
input transistor is operably coupled to receive a 1
st
input logic signal, which may be one phase of a first differential input signal. The 2
nd
input transistor is coupled in parallel with the 1
st
input transistor and is further coupled to receive a 2
nd
input logic signal, which may be one phase of a 2
nd
differential input signal. The complimentary transistor is operably coupled to the sources of the 1
st
and 2
nd
input transistors and to receive a complimentary input signal. The complimentary input signal mimics the other phase of the 1
st
differential logic signal and the 2
nd
differential logic signal.
The current source is coupled to sink a fixed current from the 1
st
and 2
nd
input transistors as well as from the complimentary transistor. The 1
st
load is operably coupled to the drains of the 1
st
and 2
nd
input transistors and to a 2
nd
potential. The coupling between the 1
st
load and the drains of the 1
st
and 2
nd
input transistors provides a 1
st
leg, or phase, of a differential logic output. The 2
nd
load is coupled to the drain of the complimentary transistor and to the 2
nd
potential (e.g., V
DD
). The coupling between the 2
nd
load and the drain of the complimentary transistor provides a 2
nd
leg, or phase, of the differential logic output.
The high speed differential signaling logic gate may be configured to implement a NOR function, OR function, NAND function, or AND function based on the differing configurations of utilizing the phases of the 1
st
and 2
nd
differential input signals as well as the different phases for the differential output. For example, a NOR function may be obtained when the positive leg of the differential input signal is coupled to the 1
st
input transistor and the positive leg of the 2
nd
differential input signal is coupled to the 2
nd
input transistor. The 1
st
leg of the differential logic output is the positive leg of a differential NOR output and the 2
nd
leg of the differential logic output is a negative leg of the differential NOR output.
Another embodiment of a high speed differential signaling combinational logic circuit includes a 1
st
input transistor, a 2
nd
input transistor, a complimentary transistor, a 3
rd
input transistor, a 4
th
input transistor, a current source, a 1
st
load, and a 2
nd
load. The 1
st
and 2
nd
input transistors are operably coupled to receive one phase of 1
st
and 2
nd
differential input signals. The complimentary transistor is operably coupled to receive a complimentary input signal. The 3
rd
and 4
th
input transistors are operably coupled to receive one phase of a 3
rd
differential input logic signal. The 1
st
load is coupled to the drains of the 1
st
and 2
nd
input transistors wherein such coupling provides a 1
st
leg of a differential logic output. The 2
nd
load is coupled to the drain of the complimentary transistor wherein such coupling provides a 2
nd
leg of the differential logic output. The drain of the 4
th
input transistor is coupled to the drain of the complimentary transistor. The drain of the 3
rd
input transistor is coupled to the sources of the 1
st
, 2
nd
and complimentary transistors.
By utilizing different phases of the differential input signals and changing phases of the differential output signal multiple combination or logic functions may be achieved. For instance, a OR/NAND function, an OR/AND function, a NAND/AND function and an AND function may be obtained through various combinations of the phases of the differential input signals and changing phases of the differential output signal.
Various embodiments of the high-speed differential signaling logic gate or combinational logic circuit may be used in a divider circuit of a local oscillator within a radio frequency integrated circuit. Other applications from the high-speed differential signaling logic gate, and/or combination of logic circuit, may be used in computers, home entertainment equipment, et cetera.
REFERENCES:
patent: 5291076 (1994-03-01), Bridges et al.
patent: 6265898 (2001-07-01), Bellaouar
patent: 6333645 (2001-12-01), Kanetani et al.
patent: 62021324 (1987-01-01), None
Broadcom
Cho James H.
Markison Timothy W.
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