High-speed differential logic buffer

Electronic digital logic circuitry – Interface – Current driving

Reexamination Certificate

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Details

C327S110000, C327S111000, C330S253000

Reexamination Certificate

active

10945323

ABSTRACT:
A circuit for a high speed digital buffer has an active load circuit connected to an output of the digital buffer. The active load circuit loads the buffer output with an active inductance to reduce the RC time constant at the buffer output. The active load circuit may be based on two active devices connected to the buffer output so as to form a differential cascode circuit.

REFERENCES:
patent: 6788103 (2004-09-01), Feldman et al.
patent: 2004/0227573 (2004-11-01), Soda
Lee, Thomas H. “High-Frequency Amplifier Design”,The Design of CMOS Radio-Frequency Integrated Circuits, 2d Ed. 2004, Chapter 9, pp. 270-276, no month.
Bui, et al “Shunt-Peaking of MCML Gates Using Active Inductors”,Circuits and Systems, 2004, NEWCAS 2004, The 2ndAnnual IEEE Northeast Workshop On Montreal, Canada Jun. 20-23, 2004, USA, IEEE, Jun. 20, 2004, pp. 361-364.
Jiang, et al “A New CMOS Class-AB Transmitter for 10 GBPS Serial Links”,Circuits and Systems, 2004, MWSCAS '04, The 2004 47thMidwest Symposium on Hiroshima, Japan, Jul. 25-28, 2004, USA, IEEE, vol. 3, Jul. 25, 2004, pp. III319-III322.
Sackinger, et al “A 3GHz, 32db CMOS Limiting Amplifier for SONET OC-48 Receivers”,International Solid-State Circuits Conference, 2000, ISSCC '00, San Francisco, USA, Feb. 7, 2000, pp. 158-159.

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