Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-04-29
2003-05-27
Beausoliel, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S029000, C714S738000, C714S742000, C703S023000, C703S024000, C703S025000
Reexamination Certificate
active
06571357
ABSTRACT:
TECHNICAL FIELD
This invention relates in general to computer system testing and in particular to testing of a computer sub-system employing an chip emulation.
BACKGROUND
When testing computer system components which are in development, various chips and other components are commonly not yet available making it impossible to test certain computer system or sub-system configurations in their final form. Accordingly, in order to test certain computer sub-systems, certain components are generally emulated in order to allow the rest of the sub-system to be operated and observed.
Generally, prior art solutions involved emulating the operation of an entire board where any portion of the board was not yet available in production form in order to enable various boards interacting with the incomplete board to be tested. This approach would generally enable boards other than the one being emulated to be tested but would generally not allow any components on the emulated board to be tested. This represents a missed opportunity since, in many cases, certain components on the board being emulated were available.
One problem arising with the prior art approach is that the equipment used to emulate a missing or incomplete board was often too physically large and cumbersome to properly interconnect with the subsystems being tested. This situation would generally prevent the test from occurring within a natural environment such as the computer case in which the ultimate computer system would be placed. A further problem with prior art interim diagnostic approaches is that pattern generators are commonly employed to transmit data to the system under test to emulate the operation of the missing equipment. The signals available from the pattern generator however, are generally much slower than those produced by the equipment being emulated. Under such circumstances, it is difficult to acquire information regarding the behavior of the system under test in response to high data transmission rates.
Accordingly, it is a problem in the art that prior art interim computer system diagnostic equipment is generally too large to operate within the same physical environment as the ultimate product being emulated.
It is a further problem in the art that prior art diagnostic equipment is generally unable to supply data transmission rates which fully exercise the system under test.
It is a still further problem in the art that prior art emulation methods emulate entire boards, thereby preventing testing of components on the board being emulated which are physically available at the time the test is conducted.
SUMMARY OF THE INVENTION
These and other objects, features and technical advantages are achieved by a system and method which emulates unavailable equipment within a computer system at a chip or IC package level, is compact enough to enable the system under test to operate in its natural operating environment, and provides data transmission speed sufficiently to properly exercise the system under test. Moreover, since the inventive system may emulate equipment at the chip level, components on the same board as the chip or device being emulated may be tested as well as equipment on other boards. The chip being emulated may be an ASIC (application specific integrated chip) or general purpose integrated chip. In a preferred embodiment, the inventive system generally connects directly into a slot where the missing ASIC or other chip would reside once a production version of the missing chip is ready, thereby providing a high level of correspondence between the test environment and actual ultimate operating environment.
In a preferred embodiment, the inventive system includes a pattern generator, a control unit having processing, timing, and memory devices or components, cabling leading to a test board, and a conductive interface, such as an interposer, for interfacing the test board to a board within the system under test.
In a preferred embodiment, the inventive system employs the pattern generator to generate a sequence of test patterns at a speed typical of the pattern generator and stores the test patterns in memory equipment (or data storage equipment) within the control unit or control system. Once a complete set of test patterns is loaded into memory, the control system operates to transmit the stored test patterns from the control unit data storage toward the system under test at a higher frequency than that provided by the pattern generator. In this manner, the pattern generator may be beneficially employed to provide the information contained in the test patterns and separate equipment may then transmit the stored data at rates exceeding the transmission capabilities of the pattern generator in order to more fully exercise the system under test. Equipment is deployed which may transmit the stored test patterns out of memory at a selected multiple of the frequency at which the test pattern data is initially stored in the control unit memory.
Accordingly, it is an advantage of a preferred embodiment of the present invention that the system under test may operate in its normal operating environment during diagnostic operations.
It is a further advantage of a preferred embodiment of the present invention that equipment on the board housing the emulated device may be tested in addition to equipment on other boards in the system under test.
It is a still further advantage of a preferred embodiment of the present invention that data patterns may be transmitted at a high enough frequency to more fully exercise the operation of the system under test than did systems of the prior art.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present invention.
BRIEF DESCRIPTION OF THE DRAWING
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which:
FIG. 1
depicts an overall view of the equipment associated with the test apparatus according to a preferred embodiment of the present invention;
FIG. 2
is a block diagram of the functional components of the test apparatus according to a preferred embodiment of the present invention;
FIG. 3
depicts one mechanism for coupling test apparatus to the system under test according to a preferred embodiment of the present invention;
FIG. 4
is a circuit diagram for providing high frequency data patterns to a system under test according to a preferred embodiment of the present invention; and
FIG. 5
depicts computer apparatus adaptable for use with a preferred embodiment of the present invention.
REFERENCES:
patent: 4727312 (1988-02-01), Fulks
patent: 4951283 (1990-08-01), Mastrocola et al.
patent: 5889936 (1999-03-01), Chan
patent: 6223148 (2001-04-01), Stewart et al.
patent: 6289472 (2001-09-01), Antheunisse et al.
Basham Everett
Martin Matthew A.
Price Christopher D.
Beausoliel Robert
Maskulinski Michael
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