High speed decoder without race condition

Details High speed decoder without race condition High speed decoder without race condition

1996-12-20

2000-02-01

Santamauro, Jon

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

326121, H03K 19084

Patent

active

060207639

ABSTRACT:
A self-clocked apparatus for eliminating race condition in high speed decoders is provided. In multi-stage decoders, a first stage is generally composed of predecoder blocks while a second stage is generally composed of decoder/driver blocks. Each predecoder block receives several address bits and outputs a high or low level signal depending on the address bit's state. Each decoder/driver block receives the output signal of the corresponding predecoder block, and outputs a signal selecting or not selecting a connected line. The self-clocked apparatus of the invention is cross-connected between adjacent predecoder blocks such that the ith decoder/driver block is controlled by the i+1th predecoder block, and conversely. No external clock signal is used, and no time margins are required. Furthermore, the invention provides a robust electrical design.

REFERENCES:
patent: 4748597 (1988-05-01), Saito et al.
patent: 4916334 (1990-04-01), Minagawa
patent: 4958319 (1990-09-01), Von Basse et al.
patent: 5018108 (1991-05-01), Maruyama
patent: 5311479 (1994-05-01), Harada
patent: 5327026 (1994-07-01), Hardee et al.
patent: 5432744 (1995-07-01), Nagata
patent: 5469391 (1995-11-01), Haraguchi

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