Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2008-05-06
2008-05-06
Shin, Christpher (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S110000, C710S027000
Reexamination Certificate
active
07370131
ABSTRACT:
A CAN module receives a message from a CAN bus to store the same in a message box unit of a message box. A reception request signal is output from the message box unit to a DMAC/IF. The DMAC/IF outputs a 7-bit encoded address together with a transfer request signal. A DMAC accesses a selected message box unit of the CAN module and a memory based on the transfer request signal and the 7-bit encoded address to transfer the message stored in the selected message box unit to the memory.
REFERENCES:
patent: 5509127 (1996-04-01), Datwyler et al.
patent: 6654385 (2003-11-01), Odaka et al.
patent: 6901469 (2005-05-01), Ito
patent: 2006/0271694 (2006-11-01), Matsuo et al.
patent: 2007/0159489 (2007-07-01), Knepper
patent: 2007/0230484 (2007-10-01), Hu et al.
patent: 6-161947 (1994-06-01), None
patent: 11-85683 (1999-03-01), None
patent: 2000-148661 (2000-05-01), None
Ikenobe Takahiro
Inoue Hideo
Minematsu Isao
McDermott Will & Emery LLP
Renesas Technology Corp.
Shin Christpher
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