High speed data capture circuit for a digital device

Details High speed data capture circuit for a digital device High speed data capture circuit for a digital device

2001-02-23

2003-07-08

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S189050, C365S189080

Reexamination Certificate

active

06590795

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the circuitry used to capture data entering a high speed digital device, for example, a high speed memory device.
BACKGROUND OF THE INVENTION
On high speed digital devices, for example, high speed memory devices, one of the more difficult specifications to guarantee is data input setup and hold time. The difficulty stems from an inability to exactly time an arriving data capture clock with arriving data signals appearing at each capture latch. In general, the incoming clock is distributed in some form, e.g., clock distribution circuitry, so that the clock signal appearing at each capture latch has the same phase (timing). The clock distribution circuitry introduces a finite delay to the clock such that the clock and data, as they appear at the latch, do not have the same timing relationship as they had at the device input terminals. Historically, designers have either resorted to one of two approaches to correct this problem. The first is to add some form of delay to the data signal before it enters the latch. Ideally, this delay matches the amount of delay experienced by the clock signal as it propagates through the clock distribution circuitry. In general the delay circuit only approximates the actual delay. The second approach employs a delay lock loop (DLL) to add additional delay to the clock such that it appears at the latch with the correct timing relative to the data. The amount of additional delay is adjusted with feedback to account for the clock distribution delay and any additional delays due to miscellaneous Input/Output (I/O) circuits. In most cases, the clock that appears at the latch will be delayed by N x (clock period), where N is an integer. As a result, a given data bit will be captured by a clock edge which preceded the data bit by multiple clock cycles. The use of a DLL is disadvantageous for a high speed memory device needing tight (low tolerance) setup and hold times for several reasons. First, the DLL introduces additional jitter to the clock signal, which reduces the accuracy of the clock timing. Second, since the clock edge which captures the data is not the same clock edge that was transmitted with that data and cycle-to-cycle jitter problems may be introduced into the capture timing. If the data is captured with the concurrent clock edge, then cycle to cycle jitter can be ignored in the setup and hold budget. Also, a DLL introduces some timing uncertainty since it relies upon the matching of an I/O model to actual I/O circuits. Furthermore, the DLL is not able to track out instantaneous changes in delay of the clock or data circuits since it may not see these changes or it may be too slow to correct for them.
Accordingly, conventional capture circuitry using DLL or other clock distribution may not perform well in high speed memory devices which have tight set up and hold times.
SUMMARY OF THE INVENTION
The present invention provides an improved method and apparatus for capturing data in high speed digital devices, e.g., memory devices which does not require use of a DLL to properly time the arrival of the clock and data at a data capture latch.
In one aspect of the invention, a data capture circuit for a digital device, e.g., a memory device, is provided in which the capture clock and data signal are respectively routed from an incoming clock terminal (or a clock buffer) and an input data terminal (or a data buffer) to each capture latch in a point-to-point fashion with approximately the same signal path length from each of the terminals to the latch. For multiple data inputs, the path length between the clock input terminal (or clock buffer) and a latch associated with a data input and between the latch and the data input terminal (or data buffer) are approximately equal for each latch, and the path lengths for all the data capture latches may be approximately equal or unequal.
In another aspect of the invention, the latch is physically located on a digital die at a position which is approximately midway of the physical distance between a clock terminal (or clock buffer) and data terminal (or data buffer) of the memory device.
These and other advantages and features of the invention will be more clearly recognized from the following detailed description which is provided in connection with the accompanying drawings.


REFERENCES:
patent: 5163092 (1992-11-01), McNesby et al.
patent: 5689539 (1997-11-01), Murakami
patent: 5786800 (1998-07-01), Gyouten
patent: 2000 049575 (2000-02-01), None
patent: 2000 235363 (2000-08-01), None
patent: 20001 034647 (2001-02-01), None

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