High speed cyclic redundancy check algorithm

Details High speed cyclic redundancy check algorithm High speed cyclic redundancy check algorithm

1996-11-12

2000-10-03

Chung, Phung N.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

714758, 714757, 714752, G06F 1110

Patent

active

061287660

ABSTRACT:
A method of determining an error detection code (EDC) on incoming data which includes a reserved bit field, comprising applying the incoming data to inputs of both an input data CRC (IDC) calculator and to an input data and reserved field CRC (IDRC) calculator, calculating the EDC on successive input data words and recursively updating the EDC in both the IDC and IDRC calculators, selecting a payload of the input data as a system output signal for all payload words, and subsequently selecting a output EDC word from the IDRC calculator in a time immediately following a final payload word which contains the reserved field.

REFERENCES:
patent: 3753225 (1973-08-01), Liddell
patent: 5369649 (1994-11-01), Murayama et al.
patent: 5661722 (1997-08-01), Miyagi

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