High speed configuration independent programmable macrocell

Details High speed configuration independent programmable macrocell High speed configuration independent programmable macrocell

1998-03-24

2002-03-12

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

C326S040000, C326S050000, C326S097000, C327S203000

Reissue Patent

active

RE037577

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of programmable logic devices, and more particularly to a high speed programmable macro cell with a propagation delay independent of the configuration.
BACKGROUND OF THE INVENTION
In general, programmable logic devices (PLDs) permit a user to configure the PLD device to accommodate a wide spectrum of applications. One type of PLDs has a programmable macro cell. The programmable macro cell provides the capability of defining the architecture of each output individually. Each of the potential outputs may be specified to be “registered” or “combinatorial”. In addition, the polarity of each output may also be individually selected allowing complete flexibility of the output configuration. In addition, further configurability is provided through “array” configurable “output enable” for each potential output. This feature allows the outputs to be reconfigured as inputs on an individual basis, or alternatively, used as a combinational I/O controlled by the programmable array. An example of such a PLD device is manufactured by Cypress Semiconductor Corporation, the Assignee of the present invention.
FIG. 1
illustrates a user configurable macro cell configured in accordance with the prior art. For the circuit illustrated in
FIG. 1
, the user selects the configuration of the macro cell to operate as either a D-type flip-flop or a T-type flip-flop. In addition, the user selects the polarity of the output data (e.g. whether the output of the circuit is selected from the register true (Q) or bar ({overscore (Q)})). Typically, the user selects the configuration by programming user configurable bits. In response to the user configurable bits, a D-type, a T-type, a polarity, {overscore (Dtype)}, a {overscore (Ttype)} and {overscore (polarity)} select signals are generated. A macrocell
100
receives the D-type, T-type, polarity, {overscore (Dtype)}, {overscore (Ttype)} and {overscore (polarity)} select signals.
The macro cell circuit
100
contains an exclusive OR gate (XOR)
102
, a register
120
, and a plurality of transmission gates
105
,
110
,
152
and
154
. The XOR gate
102
implements the toggle function for the T-type flip-flop. As is shown in
FIG. 1
, transmission gates
105
,
110
,
115
,
125
,
140
,
148
,
154
and
152
contain a p channel metal oxide semiconductor (MOS) transistor and an n channel MOS transistor. The register
120
, used to implement the D-type and the T-type flip-flops, contains a master latch, a slave latch and a transmission gate
140
used to couple the master latch and the slave latch. The master latch includes inverters
130
and
135
, as well as transmission gate
125
. The slave latch includes inverters
145
and
146
, as well as transmission gate
148
.
The “Data In” is input to the XOR
102
and a transmission gate
105
. If a D-type flip-flop is specified by the static control signals, then the transmission gate
105
conducts the “data in” signal to a transmission gate
115
. If the static control signals specify a T-type flip-flop, then the output of the XOR gate
102
is coupled to the transmission gate
115
via the transmission gate
110
.
During a clock transition from a high state to low logic state, the data input to transmission gate
115
is passed to the master latch. Also, during the high state to low logic state transition, the transmission gates
125
and
140
are
closed

disabled
, and the transmission gate
148
is
open

enabled
to latch or retain the state previously latched in the slave latch. When the clock cycle transitions to a high logic level, the transmission gate
140
and the transmission gate
125
are
opened

enabled
to latch the data in the master latch, and to pass the data into the slave latch, inverters
145
and
146
. In addition, in the high clock cycle, the transmission gate
148
is
closed

disabled
. The polarity and {overscore (polarity)} static signals select either the true or bar outputs of the register
120
to generate the “data out”.
Although the macro cell circuit
100
provides selectable D-type or T-type configurations, the T-type configuration requires a longer set-up time than the D-type configuration due to the XOR gate
102
. In addition, the data path for the D-type configuration includes transmission gate
105
, and the data path for the T-type configuration includes transmission gate
110
. Furthermore, whether the T-type or D-type configurations are selected, the data is further delayed by the transmission gates
152
and
154
utilized to select the polarity.
SUMMARY AND OBJECTS OF THE INVENTION
Therefore, it is an object of the present invention to reduce the propagation delay of the data path in a user configurable circuit.
It is another object of the present invention to provide a high speed user configurable circuit, wherein the propagation delays are independent of the configuration.
These and other objects are included in a circuit that contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the data path circuit is independent of the user configurable inputs.
The clock logic receives the user configurable inputs and a clock input. In turn, the clock logic generates conditional clock signals to implement the logic function for the circuit based on the clock input and the user configurable inputs. The switching element includes at least one transmission gate that is controlled by the conditional clock signals. The transmission gate includes any type of pass gate, such as a three state inverter or a switching transistor. The switching element generates a logic output, in accordance with the conditional clock signals, to implement the logic function by controlling propagation of the input signal through the transmission gate. The data path circuit receives the logic output, and is also controlled by the conditional clock signals.
The circuit of the present invention has application for use as a macro cell for a programmable logic device. In one embodiment, the data path circuit is a storage element, and the user configurable inputs include a D-type register select, a T-type resister select, a latch select, and a polarity select. The logic functions implemented in the clock logic are a multiplexer function, for selecting among a D-type flip-flop, a T-type flip-flop and a latch, and a polarity function for generating a true or a bar output for the circuit. The storage element is configured as a master/slave flip-flop, and includes a master latch, that receives the logic output, and a slave latch that couples the master latch to the circuit output.
Other objects, features and advantages of the present invention will be apparent from the accompanying drawings, and from the detailed description that follows below.


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