Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
2000-04-11
2001-12-11
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C438S304000, C438S305000
Reexamination Certificate
active
06329230
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor devices and more particularly to a high-speed compound semiconductor device having an LDD (lightly doped drain) structure in combination with a low-resistance electrode provided on a gate electrode.
A compound semiconductor device having a gate electrode of a refractory metal has an advantageous feature of high operational speed and is used extensively in compound semiconductor integrated circuits for use in ultra-high frequency applications such as mobile telephony. A representative example of the mobile telephony includes portable telephones. Further, such a compound semiconductor device is advantageous in that the diffusion region can be formed relatively easily by a self-alignment process. Further, the feature of using a refractory metal for the gate electrode is advantageous in conducting a thermal diffusion process for forming a diffusion region.
Meanwhile, with the development of telecommunication technology, the analog devices and digital devices used in such ultra-high frequency applications are required to have the feature of higher operational speed and lower power consumption.
The desired increase of the operational speed is most conveniently achieved by reducing the gate length of the compound semiconductor device. On the other hand, such a decrease of gate length invites the problem of increase in the gate resistance as a result of the decrease of the cross-sectional area of the gate electrode associated with the device miniaturization. While it is generally practiced in the art to use a refractory metal silicide such as WSi for the material of the gate electrode in view of high-quality Schottky contact formed between the refractory metal silicide and a compound semiconductor substrate and further in view of the refractory nature of the refractory metal silicide, it is nevertheless desired to reduce the resistivity of the refractory metal silicide gate electrode further. It should be noted that WSi has a relatively large resistivity of about 2×10
−4
&OHgr;·cm. A similar situation holds also in other silicides of refractory elements. Further, in such a high-speed semiconductor device having a reduced gate length, it is desired to employ the so-called LDD structure for suppressing the problem of short channel effect.
In order to reduce the gate resistance in such high-speed compound semiconductor devices, there is a proposal to construct the gate electrode in two layers, the first layer being a Schottky electrode layer and the other layer being a low-resistance layer. In one example, it is proposed to form the low-resistance layer on a WSi Schottky electrode layer after conducting a thermal annealing process such as a thermal diffusion process. Alternatively, there is a proposal to deposit a WSi Schottky electrode and a low-resistance layer consecutively to form a substantially single electrode having a multiple layer structure.
In the former approach, it is possible to use a low-melting metal such as Au for the low-resistance layer. On the other hand, this former approach has a drawback in that the number of fabrication steps of the semiconductor device is increased substantially as a result of the addition of the process of forming the low-resistance layer separately from the process of forming the Schottky electrode.
In the latter approach, on the other hand, it is possible to form the multiple-layer gate structure by a single patterning process and the fabrication of the semiconductor device is conducted similarly to the case of using a single-layer gate electrode. On the other hand, the latter approach has a drawback in that there tends to occur a thermal stress in the gate electrode as a result of the difference in the thermal expansion coefficients between the Schottky electrode and the low-resistance layer, while such a thermal stress induces a deterioration in the FET performance of the device. Further, the thermal stress tends to cause an exfoliation of the low-resistance electrode layer from the Schottky electrode layer.
In order to overcome the foregoing problems of the latter approach, there is a further proposal, as disclosed in the Japanese Laid-Open Patent Publication 2-234442, to interpose a stress-relaxation layer between the low-resistance electrode layer and the Schottky electrode layer.
FIGS. 1A-1D
show the fabrication process of a MESFET according to the disclosure of the foregoing Japanese Laid-Open Patent Publication 2-234442.
Referring to
FIG. 1A
, a GaAs layer
2
of the n-type is formed on a semi-insulating GaAs substrate
1
by an MOVPE process or an MBE process, and a Schottky electrode layer
3
of WSi and a stress-relaxation layer
4
of LaB
6
are deposited consecutively on the GaAs layer
2
. Further, a low-resistance layer
5
of W is deposited on the stress-relaxation layer
4
.
Next, in the step of
FIG. 1B
, the low-resistance layer
5
of W is patterned to form a W pattern designated hereinafter by the reference
5
, on the stress-relaxation layer
4
, and an ion implantation process of Si
+
is conducted, in the step of
FIG. 1C
, into the GaAs substrate
1
through the LaB
6
stress-relaxation layer
4
and further through the WSi Schottky electrode layer
3
, while using the W pattern
5
as a mask. The Si ions thus introduced are activated by a thermal diffusion process, wherein the thermal diffusion process is conducted in the state that the WSi layer
3
and the LaB
6
layer
4
cover the substrate
1
. As a result of the thermal diffusion process, diffusion regions
6
of the n-type are formed in the substrate
1
.
In the step of
FIG. 1D
, the stress-relaxation layer
4
of LaB
6
is patterned by an ion milling process using Ar, and the WSi Schottky electrode layer
3
is patterned by a dry etching process while using the LaB
6
stress-relaxation layer
4
and the W low-resistance layer
5
thereon as a mask. Further, ohmic electrodes
7
are formed in ohmic contact with the diffusion regions
6
at both lateral sides of the gate structure that includes the stacking of the WSi Schottky electrode layer
3
, the LaB
6
stress-relaxation layer
4
and the W low-resistance layer
5
.
In the conventional process of
FIGS. 1A-1D
, on the other hand, there arises a problem in that the formation of the LDD structure in the substrate
1
is difficult.
In the process of
FIGS. 1A-1D
, it should be noted that an n
+
-type region is formed in the p-type substrate
1
in correspondence to the source and drain regions when forming an n-channel FET, while it should be noted that such a structure, characterized by a sharp change of impurity concentration level between the p-type region of the substrate
1
and the diffusion region
6
, tends to suffer from the problem of hot carrier formation during the FET operation as a result of the large electric field induced in the vicinity of the drain edge. When this problem occurs, the operational performance of the FET is deteriorated inevitably.
In order to overcome the foregoing problems, it is practiced to use an LDD structure in the FETs having such a short gate length, wherein an LDD structure includes an n
−
-type region having a reduced impurity concentration level between the p-channel region of the substrate
1
and the n
+
-type diffusion region
6
for relaxing the concentration of the electric field. Such an LDD structure is essential in such a high-speed FET having a short gate length for suppressing the short channel effect.
In the foregoing conventional process, on the other hand, the impurity ions are injected into the substrate
1
through the WSi Schottky electrode layer
3
and the LaB
6
stress-relaxation layer
4
. In such a process, it should be noted that the process window for an appropriate acceleration energy of ion implantation is extremely small, and a minute deviation in the film thickness of the layers
3
and
4
induces a substantial deviation in the thickness of the junction formed in the substrate
1
. This means that the foregoing conventi
Armstrong Westerman Hattori McLeland & Naughton LLP
Fujitsu Quantum Devices Limited
Lindsay Jr. Walter L.
Niebling John F.
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