High speed comparator for 10G SERDES

Details High speed comparator for 10G SERDES High speed comparator for 10G SERDES

2006-11-14

2006-11-14

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error count or rate

C714S707000, C714S775000

Reexamination Certificate

active

07137046

ABSTRACT:
An error counter including receive logic to compare transmitted bits with received bits and output a vector with a logic 1 for every bit that does not match and a logic 0 for every bit that matches. A plurality of stages are sequentially arranged. Each stage includes a plurality of carry save adders inputting three inputs and outputting a sum bit and a carry bit, the carry save adders of a first stage each receiving corresponding three bits of the vector as input, the carry save adders of stages subsequent to the first stage each receiving corresponding three bits representing sum bits and carry bits from the previous stage and each carry save adder outputting a carry bit and a sum bit to a next stage for use as inputs to the carry save adders of the next stage. A synchronizer converts an output of the stages into an N-bit sum.

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patent: 6424189 (2002-07-01), Su et al.
patent: 2004/0153913 (2004-08-01), Fishman et al.

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