High-speed CMOS pseudo-ECL output driver

Details High-speed CMOS pseudo-ECL output driver High-speed CMOS pseudo-ECL output driver

1994-06-01

1996-08-20

Westin, Edward P.

Electronic digital logic circuitry

Interface

Logic level shifting

326 88, 341136, H03K 190175

Patent

active

055482309

ABSTRACT:
A complementary metal oxide silicon (CMOS) data to emitter coupled logic (ECL) data translator system comprised of translator apparatus for receiving data signals from a CMOS circuit powered from a CMOS voltage power source, apparatus for powering an ECL circuit from the power source, a transmission line carrying output signals from the translator apparatus to the ECL circuit, having a predetermined characteristic, a load having the characteristic impedance connecting the transmission line to the power source, and the translator apparatus comprising apparatus for outputting a data signal on the transmission line which corresponds to the received data signals but having an amplitude compatible with the ECL circuit and referenced to a voltage of the power source.

REFERENCES:
patent: 4704549 (1987-11-01), Sanwo et al.
patent: 5074671 (1991-09-01), Suthar et al.
patent: 5105102 (1991-02-01), Shioda
patent: 5216297 (1993-06-01), Proebstring
Steyart et al; "ECL-CMOS and CMOS-ECL Interface in 1.2 .mu.m CMOS For 150-MHz Digital ECL Data Transmission Systems"; IEEE Journal of Solid-State Circuits; vol. 26, No. 1; Jan. 1991; pp. 18-24.

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