High speed CMOS dual modulus prescaler using pull down...

Details High speed CMOS dual modulus prescaler using pull down... High speed CMOS dual modulus prescaler using pull down...

2003-01-07

2004-02-24

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

C337S047000, C337S048000, C327S115000

Reexamination Certificate

active

06696857

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the design of high-speed prescaler circuits. More particularly, this invention relates to a circuit and a method for creating high-speed CMOS dual modulus prescalers using pull-down transistors.
2. Description of the Prior Art
There have been few attempts in the past for the CMOS design of high-speed dual modulus prescalers where low power consumption and high speed have been considered the stringent requirements. The speed of these prescalers gets further degraded due to additional loads from gates and flip-flops to achieve high divided-by-value. In general, the speed of the prescalers consisting of high-speed synchronous counters is limited by the delay of feedback critical paths. In the prior art, in most cases, logic gates are used in the feedback critical/paths.
U.S. Pat. No. 6,369,623 B1 (Heinen) “Circuit Configuration for a Frequency Divider” describes a frequency divider with a prescaler which includes two dual modulus dividers.
U.S. Pat. No. 6,067,339 (Knapp et al.) “Frequency Divider with Lower Power Consumption” describes a dual modulus prescaler using flip-flops.
U.S. Pat. No. 6,219,397 (Park) “Low Phase Noise CMOS Fractional-N Frequency Synthesizer for Wireless Communications” describes a frequency synthesizer with a prescaler which includes a two modulus prescaler having at least one flip flop.
U.S. Pat. No. 6,157,693 (Jayaraman) “Low Voltage Dual-Modulus Prescaler Circuit Using Merged Pseudo-Differential Logic” describes a dual modulus prescaler using pseudo differential logic.
(Yang, et al.) “A CMOS Dual-Modulus Prescaler Based on a New Charge Sharing Free D-Flip Flop” shows a dual modulus divide by 128/129 prescaler which uses a new charge sharing dynamic D-Flip Flop for high speed and low power operation. (Craninckz, et al.) “A 1.75-GHz/3-V Dual Modulus Divided by 128/129 Prescaler in 0.7 um CMOS shows a dual modulus divide by 128/129 prescaler which uses synchronous high speed for only one divided by 2 flip flop. Synchronous means the clock goes to each flip-flop. The remainder of the prescaler uses an asynchronous divider.
(Tang, et al.) “A High-Speed Low-Power Divide-by-15/16 Dual Modulus Prescaler in 0.6 um CMOS” describes a synchronous counter which means that the clock goes to each flip-flop. The remainder of the prescaler uses an asynchronous divider. This prescaler does not have the NAND gate between stages.
(Chang, et al.) “A 1.2 GHz CMOS Dual-Modulus Prescaler Using New Dynamic D-Type Flip-Flops” describes a high speed prescaler which contains a synchronous counter and an asynchronous counter.
(Foroudi, et al.) “CMOS High-Speed Dual-Modulus Frequency Divider for RF Frequency Synthesis” describes a circuit which utilizes level-triggered differential logic to produce a low-power, high frequency circuit function.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a circuit and a method for high-speed prescaler circuits. It is further an object of this invention to provide high speed CMOS circuitry for dual modulus prescalers which utilize pull-down transistors.
The objects of this invention are achieved by a high speed CMOS dual modulus prescaler circuit made up of data or D-flip flops connected serially where the flip-flop positive output Q of stage N is connected to the D-input of the N+1 flip-flop stage. It is also made up of a P-channel metal oxide semiconductor field effect transistor, PMOS FET whose gate is connected to the negative output of a last stage of the serial chain of D-flip flops and an N-channel metal oxide semiconductor field effect transistor, NMOS FET whose drain is connected to the PMOS FET. It is also made up of a two input NAND gate whose one input is the positive output of the last flip-flop of the serial chain of D-flip flops and whose second input is a mode control signal and whose output drives the gate of the NMOS FET. A second NMOS FET has a gate which is attached to the drain of the first NMOS FET, and a second or final D-flip flop whose data input comes from the positive output of the previous D-flip flop.
The high speed CMOS dual modulus prescaler circuit has a first D-flip flop whose clock input has a frequency known as a circuit input frequency, Fin. The output of this prescaler circuit has an output frequency, Fout. The frequency division which results from this prescaler circuit is a divide by [2 to the power (n+2)] minus 1 if the mode signal
250
equals 1 as opposed to a divide by [2 to the power (n+2)] counter, which results when the mode signal
250
is low.


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Craninckz et al., “A 1.75 -GHz/3-V Dual-Modulus Divide-by-128/129 Prescaler in 0.7-&mgr;m CMOS”, IEEE Journal of Solid-State Circuits, vol. 31, No. 7, Jul. 1996, pp. 890-897.
Tang et al., “A High-Speed Low-Power Divide-by-15/16 Dual Modulus Prescaler in 0.6&mgr;m CMOS”, Analog Integrated Circuits and Signal Processing, 28, 195-200, no date, and month, 2001, Kluwer Academic Publ., pp. 195-200.
Chang et al., “A 1.2 GHz CMOS Dual-Modulus Prescaler Using New Dynamic D-Type Flip-Flops”, IEEE Jrnl. of Solid State Circuits, vol. 31, No. 5, May 1996, pp. 749-752.
Foroudi et al., “CMOS High-Speed Dual-Modulus Frequency Divider for RF Frequency Synthesis”, IEEE Jrnl. of Solid-State Circuits, vol. 30, No. 2, Feb. 1995, pp. 93-100.
Yang et al., “A CMOS Dual-Modulus Prescaler Based on a New Change Sharing Free D-Flip-Flop”, IEEE 2001, pp. 276-280.

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