Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Converging with plural inputs and single output
Reexamination Certificate
2001-03-28
2003-01-07
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Converging with plural inputs and single output
C327S112000
Reexamination Certificate
active
06504419
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to high speed closed loop multiplexer circuits for analog and digital video and communications signals.
Perhaps the closest prior art is U.S. Pat. No. 4,572,967 (Metz), which discloses a bipolar analog multiplexor circuit that includes three analog inputs, one of which is selected to be switched to an analog signal output conductor
32
in response to one of three switch control signals. Each analog input is coupled to the base of one transistor of a differential pair of emitter-coupled transistors. The switch control signals operate to “select” one of the differential pairs by connecting its emitters to a single current source, making that differential pair operative as an amplifying stage. This type of analog switch can be referred to as a “switched gm” analog multiplexor circuit.
This type of prior art analog multiplexor circuit has the problem that it provides a very poor slew rate. That is, the output current provided to a capacitive load is inadequate to rapidly charge the capacitive load in response to a fast transition of the analog input signal. The slew rate is limited by the above mentioned single current source. Other references of interest include U.S. Pat. No. 4,367,419 (Yazawa et al.), U.S. Pat. No. 5,686,974 (Nayebi et al.), U.S. Pat. No. 3,638,131 (Sarkissian), U.S. Pat. No. 3,783,307 (Breuer) and U.S. Pat. No. 4,349,750 (Geurts).
The prior art technique of using a number N of open-loop buffers to switch one of N inputs to a selected output has the shortcoming that in order to achieve an appreciable output current, the output transistors have to be large, and since the N transistors are connected in parallel, the output capacitance becomes unacceptably large. An alternative technique of having one of N open-loop buffers followed by an amplifier has the shortcoming that this technique makes it very difficult to simultaneously provide suitable bias current, slew rate, bandwidth, and noise performance. Also, for large arrays, the capacitive loading for even small-geometry output transistors becomes excessive.
Prior multiplexor circuits commercially available from Analog Devices, Inc. can be obtained in 8 by 8 array configurations and in 16 by 16 array configurations. These devices use a switched gm architecture, and have poor channel-to-channel isolation of unselected inputs from the selected output, and also have the problems of very poor output slew rates and very poor load driving capability.
There has long been a need for very high-speed linear switching or multiplexing of video signals and both digital and analog communication signals. However, at the present time only high-speed multiplexor circuits having open-loop architectures or switched gm architectures have been available. Unfortunately, multiplexor circuits with open-loop switches are very non-linear when any significant load is driven, and multiplexor circuits with switched gm stages are linear but have very poor slew rates.
Thus, there remains an unmet need for a very high-speed linear multiplexer circuit for multiplexing video signals, analog communication signals, and digital communications signals. Further, there remains an unmet need for such a very high-speed linear multiplexor circuit that is expandable to switch one of a plurality of input signals to one of a plurality of output signals without substantially decreasing bandwidth, slew rate, and load driving capability of the output stage of the multiplexor circuit.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a very high-speed linear multiplexer circuit for switching video signals, analog communication signals, and digital communication signals.
It is another object of the invention to provide a very high-speed linear multiplexer circuit which provides a high output slew rate.
It is another object of the invention to provide a very high-speed linear multiplexer circuit which provides the combination of high bandwidth and high slew rate.
It is another object of the invention to provide a very high-speed linear multiplexer circuit which provides the combination of high bandwidth, high slew rate, and high load driving capability.
It is another object of the invention to provide a very high-speed linear multiplexor circuit having high bandwidth, high slew rate, high load driving capability, and also having the capability of being expandable to form an array including a plurality of selectable inputs any one of which can be switched to any one of a plurality of selectable outputs, with little degradation of performance.
Briefly described, and in accordance with one embodiment thereof, the invention provides a circuit (
10
A,B) for multiplexing a selected one of a plurality of input signals to an output conductor (
20
). A plurality of input buffers (
11
-
1
,
2
. . . N) each have an input terminal coupled to receive an input signal (Vin
1
,
2
. . . N), respectively, and each input buffer has a low impedance output terminal (
21
). Switched bias current circuitry (
100
) is coupled to the input buffers for providing an operating (+) bias current and an operating (−) bias current for a selected one of the input buffers in response to a selection control signal (INi) and also for preventing flow of operating (+) bias current and operating (−) bias current in the input buffers which are not presently selected. An output buffer (
16
) includes an output coupled to the output conductor (
20
), an input (
17
), and first (
18
) and second (
19
) bias terminals. A feedback resistor (RFB) is coupled between the output conductor (
20
) and the low impedance outputs (
21
) of the input buffers (
11
). A first current mirror (
14
) includes a control input coupled to a first bias terminal (
11
C) of each of the input buffers, a first output coupled to the input (
17
) of the output buffer (
16
), and a second output coupled to the first bias terminal (
18
) of the output buffer (
16
). A second current mirror (
15
) includes a control input coupled to a second bias terminal (
11
D) of each of the input buffers, a first output coupled to the input (
17
) of the output buffer (
16
), and a second output coupled to the second bias terminal (
19
) of the output buffer (
16
).
In another embodiment, a circuit (
10
D) for multiplexing a selected one of a plurality of input signals to an output conductor (
20
) includes a plurality of diamond follower input buffers (
11
-
1
,
2
. . . N) each having an input terminal coupled to receive an input signal (Vin
1
,
2
. . . N), respectively. Each diamond follower input buffer has a low impedance output terminal (
21
), and first (
11
A), second (
11
B), third (
11
C) and fourth (
11
D) bias terminals. A first conductor (
12
) is coupled to the third bias terminal (
11
C) of the each diamond follower input buffer, and a second conductor (
13
) is coupled to the fourth bias terminal (
11
D) of each diamond follower input buffer. A diamond follower output buffer (
16
) has an output coupled to the output conductor (
20
), an input (
17
), and first (
18
) and second (
19
) bias terminals. A first current mirror (
14
) has a control input coupled to the first conductor (
12
), a first output coupled to the input (
17
) of the diamond follower output buffer (
16
), and a second output coupled to the first bias terminal (
18
) of the diamond follower output buffer (
16
). A second current mirror (
15
) has a control input coupled to the second conductor (
13
), a first output coupled to the input (
17
) of the diamond follower output buffer (
16
), and a second output coupled to the second bias terminal (
19
) of the diamond follower output buffer (
16
). The feedback resistor (RFB) is coupled between the output conductor (
20
) and the low impedance outputs (
21
) of the diamond follower input buffers (
11
). A first group of switches (S
1
,
3
. . . j) selectively enables the first bias terminals (
11
A) of the diamond follower input buffers to corresponding operating (+) bias current sources in response to
Damitio Paul G.
Halbert Joel M.
Brady W. James
Englund Terry L.
Lam Tuan T.
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
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