High speed cache management unit for use in a bridge/router

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

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Details

370392, 370401, H03M 1300

Patent

active

059789514

ABSTRACT:
A method and cache management for a bridge or bridge/router providing high-speed, flexible address cache management. The unit maintains a network address cache and an age table, searches the cache for layer 2 and layer 3 addresses from received frame headers, and returns address search results. The unit includes an interface permitting processor manipulation of the cache and age table, and supports a 4-way set associative cache to store the network addresses. A plurality of functions implemented in hardware enables software manipulation of the associated cache. Four cache operating modes are selectable. The unit can identify and select destination ports within a Load Balanced Port Group for frame forwarding. The unit utilizes Virtual LAN identification in conjunction with a MAC address for lookup in the cache. A cyclic redundancy code for each address to be looked up in the cache is used as an index into the cache. If a cache thrash rate exceeds a predetermined threshold, CRC table values can be rewritten. Four time-sliced cache lookup units are provided, each consisting of a cache lookup controller for comparing a received network address to an address retrieved from an identified cache set.

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patent: 5708659 (1998-01-01), Rostoker et al.
patent: 5742792 (1998-04-01), Yanai et al.
patent: 5802278 (1998-09-01), Isfeld et al.

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