High-speed bus with embedded clock signals

Details High-speed bus with embedded clock signals High-speed bus with embedded clock signals

2005-01-18

2005-01-18

Elamin, A. (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C710S316000, C710S305000

Reexamination Certificate

active

06845461

ABSTRACT:
A system and method for embedding at least one clock signal into bus lines that also carry data signals at other times to enable a high-speed bus is disclosed. Each bus line is used for carrying both clock and data information at different times. Data signals, which may be either encoded or not, are carried through a subset of the bus lines through a mapping scheme that maps the data information to the bus lines at each data transfer while the clock signals are carried in the remaining bus lines. Various mapping schemes are possible.

REFERENCES:
patent: 5018110 (1991-05-01), Sugiyama et al.
patent: 5025419 (1991-06-01), Nishino
patent: 5376928 (1994-12-01), Testin
patent: 6058442 (2000-05-01), Fort
patent: 6480921 (2002-11-01), Mansoorian et al.

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