High speed bus topology for expandable systems

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation

Reexamination Certificate

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C361S775000, C361S788000

Reexamination Certificate

active

06963941

ABSTRACT:
A high-speed short-loop bus topology that routes the bus into a first expansion connector and out of a first expansion card inserted within the connector is disclosed. The bus is not routed out of the first expansion connector. Instead, the bus is routed from the first expansion card into a second expansion card by a jumper mechanism. The bus is routed through the second expansion card and out of a second expansion connector housing the second expansion card, where the bus can be terminated or routed into another expansion connector having another expansion card. By routing the bus in this manner, it is shorter than prior art buses found in loop-through bus systems and capable of substantially maintaining a uniform transmission line impedance. Moreover, the operating bandwidth of the short-loop bus is increased since the bus is short and does not have stubs or signal reflections.

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Handbook of Lan Cable Testing, Bob Hoagland, 1st edition Sep. 1992.

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