Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2005-08-09
2005-08-09
Ray, Gopal C. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S112000, C710S305000, C710S240000
Reexamination Certificate
active
06928500
ABSTRACT:
A high speed bus system for use in a shared memory system that allows for the high speed transmissions of commands and data between a number of processors and a memory array of a multi-processor, shared memory system, with the high speed bus system including a central unit and a series of uni-directional buses that connect between the plurality of processors and shared memory, with the central unit including arbitration logic and a series of multiplexers to determine which CPUs are granted access to shared buses, scheduling logic that works with the arbitration logic and multiplexers to determine which CPUs are granted access to the shared buses, and port logic for combining the CPU transmissions and determining if such transmissions are valid.
REFERENCES:
patent: 4096572 (1978-06-01), Namimoto
patent: 4470114 (1984-09-01), Gerhold
patent: 4570220 (1986-02-01), Tetrick et al.
patent: 4591979 (1986-05-01), Iwashita
patent: 4737932 (1988-04-01), Baba
patent: 4807184 (1989-02-01), Shelor
patent: 4834483 (1989-05-01), Arthurs et al.
patent: 4837682 (1989-06-01), Culler
patent: 4991084 (1991-02-01), Rodiger et al.
patent: 5072363 (1991-12-01), Gallagher
patent: 5088024 (1992-02-01), Vernon et al.
patent: 5168547 (1992-12-01), Miller et al.
patent: WOA8704826 (1987-08-01), None
“Evaluation of reservation-arbitrated access schemes for statistical multiplexing of variable-bit-rate video traffic over dual bus metropolitan area networks” by Chan, H.C.B.; Leung, V.C.M. (abstract only) Publication Date: Jun. 1998.
“A SoC communication architecture with fine-grained control over bandwidths and latencies” By Xu, Ningyi; Liu Hong; Zhou Zucheng; Peng Jihu (abstract only) Publication Date: Oct. 21-24, 2003.
Derosa John
Keller James B.
Ramanujan Raj
Samaras William A.
Stewart Robert E.
Hewlett--Packard Development Company, L.P.
Ray Gopal C.
LandOfFree
High speed bus system that incorporates uni-directional... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High speed bus system that incorporates uni-directional..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed bus system that incorporates uni-directional... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3466210