High speed bus system and method for using voltage and timing os

Details High speed bus system and method for using voltage and timing os High speed bus system and method for using voltage and timing os

1998-10-02

2000-11-21

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710104, 710110, 710128, 710126, 710 33, 712 31, 712 28, 712 36, G06F 1300

Patent

active

061516481

ABSTRACT:
A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using XOR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs. The system may use a first set of oscillating references on a first bus for detecting transitions in control information and a second set of oscillating references for detecting transitions in data information.

REFERENCES:
patent: 4247817 (1981-01-01), Heller
patent: 4663769 (1987-05-01), Krinock
patent: 4745365 (1988-05-01), Ugenti
patent: 4792845 (1988-12-01), Judge
patent: 5023488 (1991-06-01), Gunning
patent: 5105107 (1992-04-01), Wilcox
patent: 5243703 (1993-09-01), Farmwald et al.
patent: 5254883 (1993-10-01), Horowitz et al.
patent: 5263049 (1993-11-01), Wincn
patent: 5319755 (1994-06-01), Farmwald et al.
patent: 5355391 (1994-10-01), Horowitz et al.
patent: 5363332 (1994-11-01), Murabayashi et al.
patent: 5378946 (1995-01-01), Reime
patent: 5408129 (1995-04-01), Farmwald et al.
patent: 5432823 (1995-07-01), Gasbarro et al.
patent: 5473575 (1995-12-01), Farmwald et al.
patent: 5473635 (1995-12-01), Chevroulet
patent: 5485575 (1996-01-01), Chess et al.
patent: 5498985 (1996-03-01), Parle et al.
patent: 5512853 (1996-04-01), Ueno et al.
patent: 5513327 (1996-04-01), Farmwald et al.
patent: 5513377 (1996-04-01), Capowski et al.
patent: 5550496 (1996-08-01), Desroches
patent: 5579492 (1996-11-01), Gay
patent: 5590369 (1996-12-01), Burgess et al.
patent: 5606717 (1997-02-01), Farmwald et al.
patent: 5638446 (1997-06-01), Rubin
patent: 5646642 (1997-07-01), Maekawa et al.
patent: 5706484 (1998-01-01), Mozdzen et al.
patent: 5715405 (1998-02-01), McClear et al.
patent: 5724425 (1998-03-01), Chang et al.
patent: 5774354 (1998-06-01), Ohta
patent: 5796962 (1998-08-01), Fant et al.
patent: 5832208 (1998-11-01), Chen et al.
patent: 5850559 (1998-12-01), Angelo et al.
patent: 5878234 (1999-03-01), Dutkiewicz et al.
patent: 5925118 (1999-07-01), Revilla et al.
patent: 5928343 (1999-07-01), Farmwald et al.
4M.times.18 SLDRAM Preliminary Data Sheet Sep. 1997 from SLDRAM Consortium.
1M.times.16.times.4 Banks DDR SDRAM Jun. 1997 from Samsung.
Kim et al. "A 640MB/s Bi-Directional Data Strobed,, Double-Data-Rate SDRAM with a 40mw DLL Circuit for a 256MB Memory System", ISSCC98 Digest pp. 158-159 Feb. 1998.
Morooka et al., "Source Synchronization and Timing Vernier Techniques for 1.2GB/s SLDRAM Interface", ISSCC98 Digest pp. 160-161 Feb. 1998.
B. Lau et al. "A 2.6GB/s/Multi-Purpose Chip-to-Chip Interface", ISSCC98 Digest pp. 162-163 Feb. 1998.
LVDS I/O (Scalable Coherent Interface Documents) IEEE P1596.3 working-group activity for high-speed signal link interface.
Hyper-LVDS I/O Cells (LSI Logic Product Briefs).
Richard Crisp, "Direct Rambus Technology: The New Main Memory Standard", Nov./Dec. 1997 issue of IEEE Micro.
Direct RDRAM 64/72 Mbit (256K.times.16/18.times.16d) , "Advance Information" of 64M/72M Direct RDRAM Data Sheet, dated Oct. 2, 1997.
Tamura et al., "PRD-Based Global-Mean-Time Signaling for High-Speed Chip-to-Chip Communications", ISSCC98 Digest, pp. 164-165 & pp. 430-432; Feb. 1998.
Griffin et al., "A Process Independent 800MB/s DRAM Bytewide Interface Featuring Command Interleaving and Concurrent Memory Operation", ISSCC98 Digest, pp. 156-157 Feb. 1998.
RamLink, LVDS I/O (Scalable Coherent Interface Documents) IEEE P1596.4 working-group activity for high-speed signal link interface.
Xilinx Application Note: "Using the Virtex SelectIO", XAPP 133 Oct. 21, 1998 (Version 1.11), 12 pages.
Web page: http://iel.ihs.com:80/cgi-bin/iel.sub.-- cgi?se . . . 2ehts%26ViewTemplate%3ddocview%5fb%2ehts, Okamoto, E. et al., "ID-Based Authentication System For Computer Virus Detection", IEEE/IEE Electronic Library online, Electronics Letters, vol. 26, Issue 15, ISSN 0013-5194, Jul. 19, 1990, Abstract and pp. 1169-1170.
"IEEE Standard For Low-Voltage Differential Signals (LVDS) For Scalable Coherent Interface (SCI)", IEEE Std. 1596.Mar. 1996, Mar. 21, 1996, XP002106653, Introduction, Contents and pp. 1-30.

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