Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1998-06-02
2001-10-23
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S027000, C326S119000
Reexamination Certificate
active
06307399
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to buffer circuits and more particularly to an output buffer circuit with improved noise immunity and speed.
2. Description of Related Art
FIGS. 1A and 1B
show two prior art output buffer circuits.
FIG. 1A
shows an output buffer circuit
5
wherein both the pull-up transistor M
11
and the pull-down transistor M
12
are NMOS transistors. M
11
has its drain connected to the power supply Vcc, its gate connected to lead
13
and its source connected to node
12
. M
12
has its drain connected to node
12
, its gate connected to lead
14
and its source connected to the ground Vss. The source of M
11
and the drain of M
12
are connected to the output terminal Q
1
of circuit
5
. Capacitor C
1
at the output terminal Q
1
represents the output load which the buffer circuit
5
drives.
To drive the output terminal Q
1
high, the buffer driver circuit
11
causes lead
13
to go high (i.e., Vcc) thereby turning on M
11
, and causes lead
14
to go low (i.e., Vss) thereby turning off M
12
. With the drain and gate of M
11
at Vcc, output terminal Q
1
is raised to Vcc minus a threshold voltage (VT). Assuming Vcc to be 5 V and the threshold voltage of M
11
to be 1 V, the output terminal Q
1
reaches a high voltage level of 4 V.
To drive the output terminal Q
1
low, the buffer driver circuit
11
causes lead
13
to go low thereby turning off M
11
, and lead
14
to go high thereby turning on M
12
.
One advantage of circuit
5
is that because the high voltage level on output terminal Q
1
is Vcc minus VT (or 4 V), the high to low transition on the output terminal Q
1
is faster as compared to the case wherein the output terminal is driven to full Vcc (or 5 V). Further, the amount of charge discharged into Vss during the high to low transition is lower. This in turn reduces the amount of noise generated on Vss. In devices with multiple output buffer circuits wherein multiple output capacitances can be discharged to Vss at the same time, the cumulative effect of the reduction in the amount of charge discharged into Vss is a significant noise reduction on Vss.
One disadvantage of circuit
5
is slow low to high transition at the output terminal Q
1
. Initially, when the output terminal Q
1
starts to rise, M
11
has 5V across both its gate to source and drain to source. However, as the output terminal Q
1
rises, the voltage across both the gate to source and drain to source reduce, causing M
11
to rapidly become weak. Thus, the output terminal Q
1
rises slowly after an initial brief rapid rise.
Circuit
50
in
FIG. 1B
is identical to circuit
5
in
FIG. 1A
except that a PMOS transistor M
110
is used as the pull-up transistor. To pull the output terminal Q
10
high, the gates of transistors M
110
and M
120
at the respective leads
130
and
140
are pulled low (to 0 V). Since M
110
is a PMOS transistor, with 0 V at its gate, the output terminal Q
10
is pulled up to the full Vcc level. To pull the output terminal Q
10
low, the gates of M
110
and M
120
are pulled high.
The advantage of circuit
50
is that the low to high transition at the output terminal Q
10
is fast. This is because the PMOS transistor M
110
has −5 V across its gate to source throughout the transition. However, this circuit suffers from the following two disadvantages: 1) a high to low transition is slower since the transition is made from full Vcc as opposed to Vcc minus VT, and 2) more noise is generated on Vss since a greater amount of charge is discharged into Vss during the high to low transition.
Accordingly, there is a need for an output buffer circuit providing fast output transitions with low ground noise.
SUMMARY
In accordance with a first embodiment of the present invention, a buffer circuit includes a first circuit for causing an output terminal of the buffer circuit to make a transition from a first voltage to a second voltage. The buffer circuit also includes a feedback circuit for increasing the rate of the transition during the part of the transition when the output terminal moves from the first voltage to a predesignated voltage, the predesignated voltage being a value between but different from the first and second voltages.
In an alternate embodiment of the first embodiment, the feedback circuit is turned off when the output terminal reaches the predesignated voltage. The buffer circuit is powered by a power supply voltage provided at a power supply terminal. The first circuit includes an NMOS transistor connected between the power supply terminal and the output terminal. The feedback circuit includes a PMOS transistor and a logic gate, the logic gate having an input terminal and an output terminal. The PMOS transistor is connected between the power supply terminal and the output terminal of the buffer circuit. The input terminal of the logic gate is connected to the output terminal of the buffer circuit, and the output terminal of the logic gate is connected to the gate of the PMOS transistor. As the output terminal makes a transition from a low voltage to the predesignated voltage, the logic gate causes the PMOS transistor to turn on when the output terminal starts to rise, and then causes the PMOS transistor to turn off when the output terminal reaches the predesignated voltage. In this manner, both the PMOS and NMOS transistors are on simultaneously, pulling the output signal to the predesignated voltage at a faster rate than if only the NMOS transistor was on. Also, with the PMOS transistor turned off after the output terminal reaches the predesignated voltage, the NMOS transistor prevents the output signal from reaching the full supply voltage level. The lower output voltage level helps increase the output high to low transition rate, as well as reduce the amount of noise generated on the ground terminal as a result of the output high to low transition.
In accordance with a second embodiment of the present invention, a buffer circuit is powered by a power supply voltage. The buffer circuit includes an output terminal and a pull-up transistor for causing a signal at the output terminal to make a transition from a low voltage to a high voltage. The buffer circuit also has a converter circuit for converting the power supply voltage to a first voltage, the first voltage being lower than the power supply voltage. The first voltage powers the pull-up transistor.
In an alternate embodiment of the second embodiment, not intended to be limiting, the time delay through the buffer circuit is measured relative to the time at which the signal at the output terminal reaches a predesignated voltage. The predesignated voltage is intermediate the high voltage and the low voltage. In this alternate embodiment, the pull up transistor is a PMOS transistor with its drain connected to the output terminal of the buffer circuit and its source connected to the first voltage. Accordingly, in a low to high output transition, the PMOS transistor causes the output terminal to reach the predesignated voltage at a faster rate than if an NMOS transistor was used. Also, a fast high to low output transition, as well as reduced ground noise, are achieved because the converter circuit limits the output high voltage level to a level lower than the supply voltage.
These and other features and advantages of the present invention will become more apparent from the following description and the accompanying drawings.
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Lien Chuen-Der
Tien Ta-Ke
Cho James H
Integrated Device Technology Inc.
Skjerven Morrill & MacPherson LLP
Tokar Michael
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