High-speed block transfer circuit

Details High-speed block transfer circuit High-speed block transfer circuit

2000-11-03

2004-01-27

Vo, Tim (Department: 2189)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S305000, C710S100000

Reexamination Certificate

active

06684286

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a high-speed block transfer circuit in dynamic bus sizing. Particularly, this invention relates to a high-speed block transfer circuit in dynamic bus sizing that is used in the CPU of a system having a high-speed external access based on an expanded bus width without changing an instruction set architecture as a design asset.
BACKGROUND OF THE INVENTION
In general, a CPU controls a system as a whole. Further, the CPU exchanges data with other devices like memories and I/O units.
Therefore, if a high-speed CPU is used it is possible to improve the performance of the whole system.
In order to meet this requirement, a structure as shown in
FIG. 10
has so far been proposed.
Legend
1
denotes a group of instruction registers IR which store instructions. Legend
2
denotes a decoder DEC which decodes the instructions issued from the IR
1
and generates internal control signals and internal data. Legend
3
denotes a group of register files REG that store the internal data. Legend
4
denotes an arithmetic logical unit ALU which performs arithmetic operation based on data received from the decoder DEC
2
and the register group REG
3
. Legend
5
denotes a programmable counter PC which displays an address of an instruction currently under execution.
Legend
6
denotes a data bus which delivers data to the outside. Legend
7
denotes an address bus for making access to the outside. Legends
8
,
9
,
10
and
11
denote data buses that are used for receiving data when making access to the outside.
A general function of the CPU is performed based on the above structure.
Legend
13
and
14
denote data address buses for connecting all the above mentioned components to external devices such as a memory
15
and an I/O unit
16
.
In general, access time slows in the order of a register within the CPU, a cache memory, an external memory, and an I/O unit.
To overcome this problem, there is a method of improving the processing speed of a system by expanding the width of the external bus, which is a completely different method from the method of improving the speed of the operation frequency of the CPU. By expanding the bus width of the external bus, the bus width after the expansion and the bus width before the expansion, as well as a bus width between these bus sizes, are dynamically changed to make it possible to exchange data at high speed. This method is called dynamic bus sizing.
When the CPU makes access to the memory and the I/O unit, the CPU uses dynamic bus sizing to exchange data between the CPU and these external units at high speed. However, when an instruction code has maintained compatibility only by expanding a bus width without changing the instruction set architecture of the CPU, it is also necessary to succeed an existing program.
Because of this background, a CPU that can process dynamic bus sizing tends to implement the instruction set in complete compatibility with the system before the expansion of the bus width or in compatibility with the system at a higher level.
This method has following drawbacks in relation to dynamic bus sizing.
FIG. 11
shows a comparison of transfers carried out using a CPU block transfer instruction. A, a CPU adapted to dynamic bus sizing in complete compatibility with the system based on the bus width expansion or in compatibility with the system at a higher level does not carry out dynamic bus sizing but carries out only transfer processing of a block transfer having the fixed data length of the original instruction.
FIG. 12
shows the operation sequence of the CPU. After an instruction has been decoded, the execution of a transfer instruction is started at step S
1
. Then, a transfer origin is read at step S
2
, a transfer destination is written at step S
4
. A register data processing is carried out at step S
5
, and a transfer end decision is made at step S
6
. Following this decision, whether a transfer is to be continued or not is decided.
When it has been decided that a transfer is to be continued, the process returns to step S
2
and the transfer origin is read again. When it has been decided that the transfer has been completed, the execution of the transfer instruction is ended at step S
7
.
At step S
2
and step S
4
, data transfer is carried out in the transfer data fixed length of the original instruction.
Usually, a block transfer data fixed length of the original instruction is shorter than a data length corresponding to dynamic bus sizing. Therefore, there is a risk that the performance is not improved when the transfer instruction of the CPU is used.
Suppose that an initial address of a block transfer origin is expressed as “HL” an, initial address of a block transfer destination is expressed as “DE”, and block transfer length is expressed as “BC”, where HL, DE and BC are all positive integers, and that the transfer processing is carried out based on these parameters. Further, suppose that the block transfer data fixed length is expressed as x [byte] and corresponding bus sizing length is expressed as y [byte]. In this case, a problem occurs under a condition of DE≦HL+(y−x) [byte] (x≠y) in a memory space that has been memory-mapped in the fixed data length of the original instruction.
FIG. 11
shows a result of carrying out a data transfer from a 16-bit data memory to a 16-bit data memory by dynamic bus sizing under the condition of DE≦HL+(y−x) [byte] (x≠y) when x=1 and y=2.
Data within the memory after a normal transfer operation is different from data within the memory after a correct transfer operation. This difference occurs because of a problem in dynamic bus sizing under the condition given.
A prior-art technique has been disclosed in Japanese Patent Application Laid-open No. 5-204836. This prior-art technique is similar to the present invention in only the processing during an overlap. The present invention is clearly different from this prior-art technique in that the present invention includes processing of dynamic bus sizing and pipeline processing of the CPU.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a high-speed block transfer circuit in dynamic bus sizing that makes it possible to carry out a block transfer in a data length of at least a block transfer data fixed length of an original instruction and that carries out a dynamic bus sizing processing.
In order to achieve the above object, the high-speed block transfer circuit is provided with a processing unit that can carry out a dummy symbol processing by using a CPU block transfer instruction based on a condition discriminant “DE≦HL+(y−x) [byte] (x≠y)” where “HL” represents an initial address of a block transfer origin, “DE” represents an initial address of a block transfer destination, “x [byte]” represents a block transfer data fixed length of an original instruction, and “y [byte]” represents a corresponding bus sizing length.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.


REFERENCES:
patent: 5423009 (1995-06-01), Zhu
patent: 5761456 (1998-06-01), Titus et al.
patent: 6047348 (2000-04-01), Lentz et al.
patent: 6101567 (2000-08-01), Kim et al.
patent: 6381664 (2002-04-01), Nishtala et al.
patent: 6434654 (2002-08-01), Story et al.
patent: 5-204836 (1993-08-01), None

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