High-speed block id encoder circuit using dynamic logic

Details High-speed block id encoder circuit using dynamic logic High-speed block id encoder circuit using dynamic logic

1995-12-29

1997-06-03

Hudspeth, David R.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

326 62, 326 93, H03K 140175

Patent

active

056358628

ABSTRACT:
A high-speed block id encoder circuit using dynamic logic includes a plurality of input signal lines received from a memory array and a plurality of output signal lines. A first portion of the encoder circuit pre-charges the plurality of output signal lines to a first state. A plurality of transistors coupled together in a single level receives the input signals and discharges the appropriate output signal lines to a second state based on the input signals. The signals produced on the output lines provide an encoded output identifying which one of the plurality of input signal lines is asserted.

REFERENCES:
patent: 4202044 (1980-05-01), Beilstein, Jr. et al.
patent: 4631428 (1986-12-01), Grimes
patent: 5557275 (1996-09-01), Van Valburg et al.
Popescu, Val, Merle Schultz, John Spracklen, Gary Gibson, Bruce Lightner and David Isaman, "The Metaflow Architecture", IEEE Micro, Jun. 1991, pp. 10-13 and 63-73.

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