High speed bidirectional bus with multiplexers

Electronic digital logic circuitry – Interface – Current driving

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326 39, 326 86, 326 90, H03K 190175

Patent

active

058475800

ABSTRACT:
A multiplexer chain is coupled to two logic gates which in turn propagate their respective output signals in different directions, thereby providing bidirectional signal distribution. The output lines of multiple multiplexer chains are combined together using a logic gate chain to create a bus line with a larger number of drivers while substantially maintaining switching speed and flexibility in routability. In one embodiment, two OR chains propagate signals in opposite directions. The top OR chain combines the outputs of all the multiplexer chains to its left. Similarly, the bottom OR chain combines the outputs of all the multiplexer chains to its right. The output of the entire bus is provided at both the leftmost and the rightmost end of the OR chain. The bus output is also provided at tap points by combining the outputs of the top logic gate chain and the bottom logic gate chain using a logic gate. The top logic gate chain provides the outputs of all drivers to the left of the tap point while the bottom logic gate chain provides the outputs of all drivers to the right of the tap point.

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"The Programmable Logic Data Book", 1996, published by Xilinx Inc., 2100 Logic Drive, San Jose, California, 95124, pp. 4-1 to 4-49.

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