High speed BiCMOS memory having large noise margin and repeatabl

Details High speed BiCMOS memory having large noise margin and repeatabl High speed BiCMOS memory having large noise margin and repeatabl

1992-02-28

1994-02-01

LaRoche, Eugene R.

Static information storage and retrieval

Systems using particular element

Semiconductive

365154, 365156, G11C 700, G11C 1140

Patent

active

052837572

ABSTRACT:
A memory that is comprised of an array of memory cells which are made of cross-coupled field effect transistors further has a novel read port to read data from the cells. This read port includes a) a respective P-channel transistor for each memory cell having a gate coupled to a set or reset node of the cell; b) each P-channel transistor in a row of memory cells has a drain coupled to a respective row line for the row of cells which is otherwise disconnected from the cells; c) each P-channel transistor has a source coupled to the base of a respective bipolar transistor; and, d) each bipolar transistor in a column of memory cells has a collector coupled to a voltage bus and has an emitter coupled via a bit line to a sense amplifier for the column. With this read port structure "1" and "0" data bits can be read from the cells with both a high speed and a high noise margin. Any number of additional read ports can be provided by simply duplicating the components a) thru d) for each such port.

REFERENCES:
patent: 4833648 (1989-05-01), Scharrer et al.
patent: 4933899 (1990-06-01), Gibbs
patent: 4984203 (1991-01-01), Shookhtim et al.
patent: 4995001 (1991-02-01), Dawson et al.
patent: 5003509 (1991-03-01), Bosnyak
patent: 5189640 (1993-02-01), Huard

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