High speed bi-MOS logic circuit operative under low power voltag

Details High speed bi-MOS logic circuit operative under low power voltag High speed bi-MOS logic circuit operative under low power voltag

1996-09-04

1999-04-13

Santamauro, Jon

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Bipolar and fet

326 18, 326108, H03K 1908

Patent

active

058942319

ABSTRACT:
First and second inverting stages and first and second decoding stages form in combination a decoder circuit, each of NAND gates of the first and second decoding stages and each of inverters of the first and second inverting stages are implemented by bi-MOS circuits, respectively, and the bi-MOS circuit for the NAND gate and the bi-MOS circuit for the inverter are a high-speed large-current consumption type and a low-speed small-current consumption type so that the decoder circuit achieves a high switching speed without sacrifice of power consumption.

REFERENCES:
patent: 4829201 (1989-05-01), Masuda et al.
patent: 4858189 (1989-08-01), Ogiue et al.
patent: 5119314 (1992-06-01), Hotta et al.
M. Minami, et al., "Base-Biased BiNMOS Circuit for Low Voltage Operation", The Institute of Electronics, Information and Communication Engineers, Technical Report of IEICE, ED93-37, ICD93-36, (1993-06), pp. 17-23. (Abstract in English).

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