Electrical computers and digital data processing systems: input/ – Intrasystem connection
Reexamination Certificate
2001-06-04
2004-09-21
Auve, Glenn A. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
C713S400000
Reexamination Certificate
active
06795882
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an apparatus and method for providing a high speed asynchronous bus for an integrated circuit. The high speed asynchronous bus of the present invention is capable of regulating the transfer of data from different clock domains of an integrated circuit.
BACKGROUND OF THE INVENTION
Large scale integrated circuits comprise many circuit elements. A large scale integrated circuit is sometimes referred to as a “microchip” or simply as a “chip.” Large scale integrated circuits often contain a number of different areas or “modules” that relate to a specific function. A module (or a group of modules) in an integrated circuit may operate on a single clock frequency. An area of an integrated circuit that operates on a single clock frequency is referred to a “clock domain.” In some cases a single module may contain two or more areas that operate on different clock frequencies. That it, a single module may contain multiple clock domains.
To regulate the transfer of data within an integrated circuit it is desirable to be able to obtain data from the different modules of the integrated circuit in an efficient manner.
SUMMARY OF THE INVENTION
The present invention is directed to an apparatus and method for providing a high speed asynchronous bus for transferring data from different clock domains of an integrated circuit.
The apparatus of the present invention comprises a high speed asynchronous data bus capable of receiving data from a plurality of modules of an integrated circuit. The high speed asynchronous data bus comprises a distributed AND structure capable of receiving a data strobe signal and a data signal from each of the plurality of modules of the integrated circuit. Each of the modules of the integrated circuit may comprise a single clock domain or may comprise multiple clock domains. The data strobe signal from each module is ANDed with each of the data strobe signals from the other modules. Similarly, the data signal from each module is ANDed with each of data signals from each of the other modules. The number of AND gates for the data strobe signals is equal to the number of AND gates for the data signals in order to minimize time delay between the data strobe signals and the data signals.
It is an object of the present invention to provide an improved apparatus and method for transferring data from different clock domains on an integrated circuit.
It is another object of the present invention to provide an improved apparatus and method for sampling data received on a high speed asynchronous bus.
It is a further object of the present invention to provide a set of improved algorithms for sampling data received on a high speed asynchronous bus.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the Detailed Description of the Invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject matter of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the Detailed Description of the Invention, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: The terms “include” and “comprise” and derivatives thereof, mean inclusion without limitation, the term “or” is inclusive, meaning “and/or”; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, to bound to or with, have, have a property of, or the like; and the term “controller,” “processor,” or “apparatus” means any device, system or part thereof that controls at least one operation. Such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document. Those of ordinary skill should understand that in many instances (if not in most instances), such definitions apply to prior, as well as future uses of such defined words and phrases.
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patent: 5442658 (1995-08-01), Cuny et al.
patent: 5561691 (1996-10-01), Weinraub
patent: 6128758 (2000-10-01), Hall et al.
patent: 6286072 (2001-09-01), Bredin et al.
Advanced Micro Devices , Inc.
Auve Glenn A.
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