High speed asynchronous and programmable state machine for...

Details High speed asynchronous and programmable state machine for... High speed asynchronous and programmable state machine for...

2005-11-29

2005-11-29

Browne, Lynne H. (Department: 2116)

Static information storage and retrieval

Read/write circuit

Serial read/write

Reexamination Certificate

active

06970392

ABSTRACT:
A state machine comprising a first input receiving a first read clock, a second input receiving a first write clock, a third input receiving a first programmable Almost Full look-ahead signal, a fourth input receiving a second read clock, a fifth input receiving a second write clock, and a sixth input receiving a second programmable Almost Full look-ahead signal is disclosed. The state machine manipulates the inputs to produce an output signal representing an Almost Full output flag that is at a first logic state when a FIFO is Almost Full and is at a second logic state when the FIFO is Not Almost Full.

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Johnie Au et al., “High Speed FIFO Synchronous Programmable Full and Empty Flag Generation”, U.S. Appl. No. 09/957,587, filed Sep. 20, 2001.
Johnie Au et al., “High Speed Asynchronous and Programmable State Machine for Generating Almost Empty Synchronous Flags in a FIFO”, U.S. Appl. No. 09/895,305, filed Jun. 30, 2001.
Johnie Au et al., “High Speed FIFO Synchronous Programmable Full and Empty Generation”, U.S Appl. No. 09/957,015, filed Sep. 20, 2001.

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