High speed array pipeline architecture

Details High speed array pipeline architecture High speed array pipeline architecture

2008-12-11

2009-11-10

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Plural use of terminal

C365S189150, C365S189160

Reexamination Certificate

active

07616504

ABSTRACT:
A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output line, the first input/output line being associated with a digitline connected to certain of the plurality of memory cells, a first read amplifier connected to the first input/output line, a first input/output device responsive to a first column select signal for connecting the first input/output line to the digitline, a second write driver connected to a second input/output line, the second input/output line being associated with the digitline, a second read amplifier connected to the second input/output line, and a second input/output device responsive to a second column select signal for connecting the second input/output line to the digitline.

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