Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Utility Patent
1997-04-25
2001-01-02
Luu, Matthew (Department: 2778)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S111000
Utility Patent
active
06169533
ABSTRACT:
The present invention relates generally to video display systems. In particular it pertains to video display systems that allow a video image to be displayed within a window on a conventional graphics image.
BACKGROUND OF THE INVENTION
Mixing of video data with graphics data can be carried out either in the digital domain or in the analog domain. If mixing is performed in the digital domain, as done by the system illustrated in
FIG. 1
, digital graphics RGB data is sent from the graphics display card
110
to the video card
120
via either the system bus (such as a PCI bus) or an advanced feature connector
114
. The video card
120
mixes digital video RGB data and the digital graphics RGB data using display hardware
124
(such as the Brooktree Bt885 video cacheDAC), where video/graphics display switching is controlled by digital color keying. In this system, when the display hardware
124
sees a digital graphics RGB datum (i.e., the 16 or 24 bits that comprise the RGB data for a single pixel) that matches the color key (a programmable value) it displays the analog video RGB data. Otherwise, it displays the analog graphics RGB data.
In add-on card applications including, but not limited to, video capture or Moving Pictures Experts Group (MPEG) systems, graphics/video mixing is commonly performed in the analog domain. Some analog mixing systems employ feature connectors while others do not. Referring to
FIG. 2
, there is shown a block diagram of a prior art analog system that employs an advanced feature connector
134
to link the graphics and video cards
110
and
140
. In such a system, the digital graphics RGB data is digitally passed to the video card
140
via the feature connector
134
along with the graphics PCLK (pixel clock) signal and graphics Hsync (horizontal synchronization) and Vsync (vertical synchronization) signals. Analog graphics RGB data is output to an analog MUX (multiplexer)
142
on the video card
140
. A video processor block
144
on the video card
140
generates a SWITCH signal when it detects a match between the color key and the digital graphics RGB data. In response to the SWITCH signal, the analog Mux
142
outputs either the analog graphics RGB data or analog video RGB data generated by the RGBDAC (RBG digital to analog converter)
145
within the analog Mux
142
.
Feature connectors have limited data bandwidth and hence limit the graphics resolutions that can be supported. Also, not every graphics card supports feature connectors. For these reasons, a feature-connector-less system for graphics/video mixing is highly desirable. Such a system is shown in FIG.
3
. Analog RGB graphics data and the Hsync and Vsync signals are coupled from the graphics card
110
to the video card
170
. To achieve the feature-connector-less requirement, a Genlock PPL (phase-locked loop)
172
is used to “genlock” the graphics and the video display cards
160
and
170
based on the Hsync and Vsync signals. Meanwhile, the color key information is detected using programmable analog window comparators
174
. As in the systems shown in
FIGS. 1 and 2
, the analog Mux
178
outputsanalog video RGB data when there is a color key match or the analog graphics RGB data when there is no match.
For sharp transitions between graphics and video display, the speed of analog comparators (such as the comparator
174
of
FIG. 3
) used for analog color key detection must be sufficiently high. Some prior art designs use high speed comparators (such as the Analog Devices AD9696) to try to satisfy the speed requirement. However, the speed with which a comparator is able to provide proper decisions is also a strong function of the difference between the two signals that it is trying to compare (i.e., faster decisions are possible for signals with greater differences). Therefore, in situations where the graphics data just before the graphics/video display interface are not constant (e.g., where the color changes along the vertical edge of the display interface) it follows that the differences between the graphics data along the interface and the predefined color key are not constant either. As a result the transition between displayed graphics and video regions does not follow a vertical straight line, as shown in
FIG. 4
, which depicts a graphics screen
210
with an embedded video window
212
. Note the rough vertical edges
214
of the video window
212
and corresponding regions of color key leak
216
, which is where patches of the color corresponding to the color key are displayed instead of the video image.
Comparators such as the AD9696 are designed using silicon bipolar technology, which is one of the factors underlying their high speed characteristics. Since CMOS devices have lower transconductance (gm) than bipolar devices for a given current the speed of a CMOS comparator is expected to be lower in general than that of an equivalent bipolar comparator. With CMOS technologies being ever more popular, many mixed signal circuits (i.e., circuits that operate on both analog and digital signals) are designed using standard CMOS techniques. Hence, it is important to derive new CMOS design techniques that allow the high speed comparisons necessary to allow sharp transitions between graphics and video display regions.
SUMMARY OF THE INVENTION
In summary, the present invention is a high speed analog color key detection technique and system that can be implemented in graphics/video systems without feature connectors while meeting the needs outlined above.
In particular, the present invention is a high speed analog color key detection system that includes a strobe comparator configured to compare each of a stream of input graphics pixel values in an input analog graphics signal to a color key value in the analog domain upon the occurrence of a predetermined state of a Strobe signal. The Strobe signal frequency is a positive integer k multiple of the frequency of a pixel clock signal that defines the rate at which the input graphics pixel values are provided. In a preferred embodiment, the integer k is a selectable positive integer (with higher values of the integer k enabling the strobe comparator to perform sub-pixel comparison for smaller parts of each of the graphics pixel values) and the Strobe signal and the pixel clock signal are synchronous. So that color key value comparisons are performed following and not during graphics pixel value transitions, the present invention can include a variable delay line that delays the Strobe signal with respect to the pixel clock signal.
The present invention can also incorporate wideband analog buffers coupled between respective input signals (with the color key value and the stream of input graphics pixel values) and the comparator to suppress kickback noise in the input signals caused by operation of the Strobe signal.
In a preferred embodiment, the color key value is defined as all values between the high and low values of color key signals coupled to the strobe comparator. The strobe comparator is configured to compare each input graphics pixel value to the color key value by determining whether the input graphics pixel value is between the high and low values and, when that is the case, asserting a MATCH signal.
The present invention can also include an analog multiplexer with data inputs coupled to an input analog video signal with a stream of pixel values and the input analog graphics signal and a select input coupled to the MATCH signal. As a result, the analog multiplexer outputs the analog video signal when the MATCH signal is asserted and otherwise outputs the analog graphics signal. A preferred embodiment can also incorporate a transmission line with a fixed delay length that is preferably set approximately (e.g., ±5 ns) equal to the delay through the strobe comparator. The transmission line is coupled between the analog graphics signal and the analog multiplexer to better align the analog graphics and video signals.
The present invention can incorporate a phase locked loop configured to generate the Strobe clock s
Chrontel, Inc.
Flehr Hohbach Test Albritton & Herbert LLP
Luu Matthew
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