Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
1999-12-20
2001-05-29
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230030, C365S230060, C365S230080
Reexamination Certificate
active
06240044
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to semiconductor devices, and more particularly to a high speed address sequencer for semiconductor devices, especially non-volatile semiconductor memory devices such as flash memory devices.
Generally, a flash memory device comprises an address sequencer, row and column decoders, sense amplifiers, write amplifiers, and a memory cell array. An example of a flash memory device is described in U.S. Pat. No. 5,490,107, the disclosure of which is herein incorporated by reference. The memory cell array contains a plurality of memory cells arranged in rows and columns. Each memory cell is capable of holding a single bit of information. A column of memory cells in the memory cell array is commonly coupled to a bit line. The column decoder, along with the address sequencer, selects a bit line. Similarly, the memory cells arranged in a row of the memory cell array are commonly coupled to a word line. The row decoder, along with the address sequencer, selects a word line. Together the row and column decoders and the address sequencer selects an individual memory cell or a group of memory cells.
The memory cells in the memory cell array of a flash memory device are generally grouped into sub-arrays called memory cell blocks. Each memory cell block is coupled to a sense amplifier and a write amplifier. The write amplifier (W/A) applies a set of predetermined voltages to the selected memory cells in order to store information. This action is referred to as a program or write operation. Similarly, a set of predetermined voltages applied to the selected memory cells allows information to be discriminated and retrieved by the sense amplifier (S/A). This action is referred to as a read operation.
During read and program operations, the address sequencer increments an address by one at a time, beginning at a starting address and ending at an ending address. Each time the address is incremented, the address is provided to the row and column buffers, respectively, which temporarily store the address.
The address stored in row and column buffers are provided to row and column decoders, respectively. The row decoder selects word lines that are associated with the address. The column decoder selects bit lines that are associated with the address. Thus, the address sequencer and the row and column decoders select one or more memory cells for a read or a program operation by selecting associated word lines and bit lines.
Since addresses are comprised of multiple address bits, generation of an address generally requires generation of a plurality of address signals. Each address signal represents a bit of the address. For example, a 21-bit address requires generation of 21 address signals. In order to generate the plurality of address signals, an address sequencer includes multiple address signal generators. Each address signal generator generates an address signal which represents one address bit.
The address sequencer typically generates the address signals in a sequential fashion, with any succeeding address signal being generated only after generation of a preceding address signal. In other words, for example, an address signal representing the k
th
address bit is typically generated only after the address signals representing first through (k−1)
th
address bits are generated. Similarly, an address signal representing a (k+1)
th
address bit is generated only after the address signals representing first through k
th
address bits are generated. For further example, an address signal representing an address bit A
5
is not generated until each address signal A
0
, A
1
, A
2
, A
3
and A
4
has been sequentially generated.
During generation of each address signal, except for the address signal A
0
representing the least significant bit, a sequential gate delay is encountered. The sequential gate delay associated with an address signal is a sum of all gate delays associated with generation of that address signal. For example, if a sequential gate delay t
a
is associated with generation of each address signal, a total amount of delay encountered during generation of address signal A
1
is at least t
a
. Similarly, total delays of at least 2t
a
, 3t
a
, 4t
a
, and 5t
a
are encountered during generation of address signals A
2
, A
3
, A
4
and A
5
, respectively.
As the generation of any one address signal, except for the address signal A
0
, requires a sequential gate delay, generation of all of the address signals making up an address requires a delay equal to a sum of all sequential gate delays. For example, if each address signal, except for the address signal A
0
, is associated with a sequential gate delay of t
a
, generation of all the address signals of a 21-bit address systems takes a total delay time of at least 20t
a
, which is equal to the sum of all sequential gate delays encountered during generation of the address signal representing the 21
st
, i.e., the most significant address bit.
The address sequencer generally operates synchronously with a clock that has an approximately constant clock frequency. A clock period of the clock is a time period between two consecutive rising edges of the clock. The clock period is 1/f seconds where f is the clock frequency in Hz. An address sequencer which operates with a clock of frequency f
0
generally completes an address increment within a clock period 1/f
0
.
Therefore, the clock period in which the address sequencer operates is generally lower bounded by the sum of all sequential gate delays associated with the address. Since address signals are generated one at a time sequentially, the sum of all sequential gate delays is approximately equal to the total delay encountered during generation of the address signal representing the most significant address bit. In other words, in order to increment an address within one clock period, the clock period must be greater than or equal to the sum of all sequential gate delays.
The sequential gate delays, therefore, are related to the delay time of generation of an address. Excessive gate delays serve to limit the size of an address for any given clock speed. Perhaps more importantly, excessive gate delays serve to limit system operational speed.
For example, if there is a 1 ns delay associated with each address signal, i.e., t
a
=1 ns, about 20 ns would be needed to generate all the address signals in a 21-bit address system. Thus, the maximum possible clock frequency that could be used with such system is about 50 MHZ, in order to complete the generation of all 21 address signals within a clock period of about 20 ns. Such a limitation is undesirable in many of today's applications where clocks with frequencies higher than 50 MHz are routinely used.
SUMMARY OF THE INVENTION
The present invention provides a high speed address sequencer that allows the use of clocks with higher frequencies.
One embodiment of the present invention is an address sequencer that receives a clock signal and generates a plurality of even and odd address signals. The address sequencer comprises a plurality of even address signal generators. The even address signal generator receives the clock signal and generates a one of the plurality of even address signals. The address sequencer further comprises a plurality of odd address signal generators. The odd address signal generator receives the clock signal and generates a one of the plurality of odd address signals.
The address sequencer further comprises a plurality of even and odd toggle logic cells. The even and odd toggle logic cells respectively receive a one of the plurality of even and odd address signals. The even and odd toggle logic cells are respectively associated with even and odd address signal generators. The even and odd toggle logic cells generate a plurality of even and odd toggle signals and a plurality of even and odd toggle address signals, respectively.
Another embodiment of the present invention is an address sequencer comprising a plurality of even address signal generators,
Christie Parker & Hale LLP
Dinh Son T.
Fujitsu Limited
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