Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2000-01-18
2001-04-17
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S193000
Reexamination Certificate
active
06219298
ABSTRACT:
RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 99-1649, filed Jan. 20, 1999, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates generally to the field of integrated circuit memory devices and, more particularly, to high-speed address decoding in integrated circuit memory devices.
BACKGROUND OF THE INVENTION
Improvements in both speed and functionality of personal computers and multimedia systems have generally resulted in accompanying improvements in memory devices to support the operation of these products. Various methods have been developed to increase the operational speed of integrated circuit memory devices. One approach to increasing the operational speed of integrated circuit memory devices may involve increasing the transmission speed of signals on data paths, such as the write data path and the read data path, which are used to write data to a memory cell and read data stored in a memory cell, respectively. It may also be desirable to decode a memory cell address at high speed to allow high-speed selection of a memory cell. In this regard, it may be particularly advantageous to decode row addresses at high speed to allow high-speed selection of a row or a word line.
With reference to
FIG. 1
, a conventional integrated circuit memory device includes a row predecoder
11
and an internal master signal generator
13
. The internal master signal generator
13
is coupled to both the row predecoder
11
and an enable signal generator
15
. The integrated circuit memory device further includes a row main decoder
17
, which is coupled to a memory cell array
19
. The row predecoder
11
and the enable signal generator
15
are both coupled to the row main decoder
17
. Operations of the integrated circuit memory device of
FIG. 1
will be described hereafter with reference to the signal timing diagram of FIG.
2
.
A row address RAi and a row address strobe signal {overscore (RAS)} (ie., external master signal) are provided as inputs to the row predecoder
11
and the internal master signal generator
13
, respectively. As shown in
FIG. 2
, the row address RAi is provided for a predetermined length of time, tAS (ie., row address setup time) before the row address strobe signal {overscore (RAS)} is activated (ie., driven to a logic 0 level). The internal master signal generator
13
, in response to the activation of the row address strobe signal {overscore (RAS)}, activates an internal master signal PR by driving the internal master signal PR to a logic 1 level. In response to the activation of the internal master signal PR, the row predecoder
11
predecodes the row address RAi and generates a predecoded row address DRAij.
After the internal master signal PR has been activated, the enable signal generator
15
allows a predetermined time interval tF to elapse before activating an enable signal PNBLS by driving the enable signal PNBLS to a logic 1 level. This delay provides the row predecoder
11
with time to generate the predecoded row address DRAij. The row main decoder
17
decodes the predecoded row address DRAij and activates a word line enable signal NWEi by driving the word line enable signal NWEi to a logic 1 level in response to the activation of the enable signal PNBLS. When the word line enable signal NWEi is activated, a corresponding word line in the memory cell array
19
is activated. Accordingly, a corresponding memory cell is selected from the memory cell array
19
.
As illustrated in the foregoing discussion, decoding a row address in a conventional integrated circuit memory device typically involves at least two time delays: First, the row predecoder
11
waits for the internal master signal generator
13
to activate the internal master signal PR before predecoding the row address RAi. Second, the enable signal generator
15
delays a predetermined time tF before activating the enable signal PNBLS to provide the row predecoder
11
with time to generate the predecoded row address DRAij. As a result , conventional integrated circuit memory devices may take a relatively long time from the point in time at which the row address {overscore (RAS)} is activated to the point in time at which the word line enable signal NWEi is activated.
Consequently, there exists a need for improved (e.g., higher speed) address decoding in integrated circuit memory devices.
SUMMARY OF THE INVENTION
High-speed address decoders may include a predecoder and a main decoder that a re both responsive to a control signal. The predecoder switches from an active state to an inactive state in response to a transition of the control signal from a first logic state to a second logic state. Conversely, the main decoder commences switching from an inactive state to an active state simultaneously with the transition of the control signal from the first logic state to the second logic state. The predecoder may generate a predecoded address signal while the control signal is in the first logic state, which may then be decoded by the main decoder to activate a line enable signal when the control signal transitions to the second logic state. As a result, address decoding speed may be improved thereby facilitating higher speed operation of an integrated circuit memory device.
In accordance with an aspect of the present invention, integrated circuit memory devices may include a predecoder and a main decoder as discussed in the foregoing. Integrated circuit memory devices may further include an internal signal generator that generates the control signal as an internal master signal in response to an address strobe signal and a memory cell array that is responsive to a line enable signal that is output from the main decoder. Because the predecoded address signal is already available when the control signal (ie., internal master signal) transitions from the first logic state to the second logic state, the main decoder can activate the line enable signal immediately upon the control signal transition.
In accordance with yet another aspect of the invention, the predecoder preferably comprises a plurality of logic gates that receive predetermined bits of the address signal at input terminals thereof, a plurality of latches that generate the predecoded address signal at output terminals thereof, and a plurality of transmission gates that are responsive to the control signal and connect the output terminals of the logic gates to the input terminals of the latches during the first logic state of the control signal.
In accordance with still another aspect of the invention, the main decoder preferably comprises a latch, a PMOS precharge transistor connected between a first reference potential (i.e., a logic 1 reference potential) and an input terminal of the latch, and a plurality of NMOS transistors electrically connected in series between the input terminal of the latch and a second reference potential (i.e., a logic 0 reference potential). The gate terminals of the NMOS transistors receive predetermined bits of the predecoded address signal from the predecoder. A control signal may be applied to the gate of the PMOS precharge transistor to charge the input terminal of the latch to a logic 1 level.
In accordance with still another aspect of the invention, both row and column addresses may be decoded. That is, the address may be either a row address or a column address and the line enable signal may be either a word line enable signal or a bit line enable signal.
Related address decoding methods are also disclosed herein.
REFERENCES:
patent: 5428577 (1995-06-01), Yumitori et al.
patent: 5485426 (1996-01-01), Lee et al.
patent: 5732040 (1998-03-01), Yabe
Hur Nak-won
Moon Byung-sick
Ho Hoal V.
Myers Bigel & Sibley & Sajovec
Nelms David
Samsung Electronics Co,. Ltd.
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