High speed address buffer for semiconductor memory

Details High speed address buffer for semiconductor memory High speed address buffer for semiconductor memory

1976-08-23

1978-02-28

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

307238, 307279, 365203, G11C 800

Patent

active

040770311

ABSTRACT:
Disclosed is an address buffer circuit for use in semiconductor memories. The buffer includes a pair of cross-coupled transistors having set and reset nodes that are precharged to a predetermined level prior to sensing the input address signals. The set and reset nodes couple to a pair of load transistors that are also precharged prior to sensing. Actual sensing occurs by further charging or discharging the set and reset nodes at rates that reflect the state of the input address signal. A current sinking circuit detects the different charge or discharge rate and selectively sinks the precharge on one load transistor thereby latching the state of the input address signal.

REFERENCES:
patent: 3959781 (1976-05-01), Mehta et al.
patent: 3983412 (1976-09-01), Roberts et al.

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