High speed add-compare-select processing

Details High speed add-compare-select processing High speed add-compare-select processing

2002-08-02

2008-10-14

Louis-Jacques, Jacques (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

07437657

ABSTRACT:
A method and apparatus for performing add-compare-select processing using carry-save arithmetic. Data compressors that operate based upon carry-save principles are utilized to render the correct result without requiring intermediate results to be resolved. Intermediate results are truncated to ensure that the dynamic range of the add-compare-select unit is not exceeded, whilst ensuring that the resolution of the intermediate results is not adversely affected. The computation of two competing paths is delayed and only the difference is computed directly, resulting in a reduction of the propagation path through the add-compare-select unit.

REFERENCES:
patent: 4757506 (1988-07-01), Heichler
patent: 5027374 (1991-06-01), Rossman
patent: 5220570 (1993-06-01), Lou et al.
patent: 5377133 (1994-12-01), Riggle et al.
patent: 5987490 (1999-11-01), Alidina et al.
patent: 6396878 (2002-05-01), Piirainen
patent: 2002/0147755 (2002-10-01), Bhushan et al.

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