High-sensitivity, self-clocked receiver for multi-chip...

Details High-sensitivity, self-clocked receiver for multi-chip... High-sensitivity, self-clocked receiver for multi-chip...

2001-03-23

2002-07-16

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Superconductor

Tunneling device

C326S001000

Reexamination Certificate

active

06420895

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to receivers for multi-chip conductor circuits, and more particularly, to high-sensitivity, self-clocked receivers providing chip-to-chip communication for superconductor integrated circuits associated with Single-Flux-Quantum (SFQ) logic.
2. Discussion of the Related Art
With recent developments in superconductor technology, more superconductor devices based on the Josephson effect are replacing conventional devices based on the semiconductor technology for high performance and low power. Digital circuits that employ the superconductor technology are often desirable because these devices enable fast logic with very low power levels, and make possible large amounts of computing power in very compact systems as compared to their semiconductor counterparts. Other benefits of superconducting devices include signal transmission with reduced signal attenuation and noise. Digital circuits that employ superconductor devices can operate at clock speeds in the 10-100 GHz range.
Increases in the circuit speed has made it very difficult to provide adequate chip-to-chip communication without any loss of signal because a receiver needs be very sensitive and asynchronous. Conventionally, Josephson transmission lines (JTL) are employed in superconductor digital circuits to provide on-chip communication and to receive narrow pulse width signals from a driver on its adjacent circuit. However, this method requires the signal transmission bandwidth to be several times the data rate. For chip-to-chip communication, bandwidth is a limiting factor.
FIG. 1
is a schematic diagram of a superconducting Josephson transmission line (JTL)
10
that is representative of receivers of the type. The JTL
10
includes a series of Josephson junctions
12
and
14
that are spaced apart at predetermined intervals along the JTL
10
. The Josephson junctions
12
and
14
are connected in parallel between a reference ground and an isolation inductor
16
, and regenerate Single Flux Quantum (SFQ) pulses at each stage when an input signal is received. The JTL
10
also includes a series of isolation inductors
16
that are connected in a series along the JTL
10
between adjacent Josephson junctions
12
and
14
to provide inductive isolation between adjacent junctions and allow propagation of the SFQ pulse. A biasing resistor
18
is connected to a current source
20
which distributes an equal amount of current to each of the Josephson junctions
12
and
14
to set the phase of each junction.
The Josephson junction
12
and
14
of the JTL
10
functions as a tunneling device including two opposing superconductive films that are separated by an oxide dielectric layer. As an input signal, or the input current impinges on a junction, the input signal splits into two signals that may have roughly equal amounts of the current. One signal goes into the isolation inductor
16
and charges the superconductive films in the associated junction. The other signal goes into the Josephson junction
12
,
14
and causes the junction to switch, or flip, its internal degree of freedom by 180°. Because the input signal splits into two signals, the input current required to flip the Josephson junction is as much as twice what would normally require a Josephson junction to flip when the current does not split into two signals. Thus, the conventional approach is susceptible only for input signals with large amounts of current, thus resulting in low sensitivity of the device.
Additionally, when the junction flips, each Josephson junction generates a voltage pulse having a fixed time integrated area, and a height determined by the characteristic of the junction. In cases where the junction carries current that is less than a predetermined threshold, the Josephson junction does not acknowledge the input current and cannot regenerate a voltage pulse. On the other hand, when the junction carries current that exceeds a predetermined threshold, the Josephson junction goes into a voltage state where it emits a pulse train or multiple voltage pulses in rapid succession although only one pulse is expected, and leads to erroneous results of the device. Therefore, it is necessary to provide a receiver that is sensitive enough to accurately acknowledge either very small or very large input currents, as well as minimizing any erroneous results.
Several attempts have been made to address the need for high receiver sensitivity by incorporating either an SFQ comparator or a quantum flux parametron. However, such device requires an external clock which makes the device synchronous and cumbersome. The synchronous device requires extra waiting periods for its signals to be transmitted because the device transmits the input signals on either the rising or falling edge of the external clock signal. In addition, some method of clock recovery or timing arbitration is required to synchronize the clock with the data. Thus, the synchronous receiver is not suitable for a high speed device. On the other hand, the asynchronous device transmits its input signals as soon as the signals arrive, thus the input signals do not have to wait for the arrival of the clock signal to be transmitted, and the timing problem is solved.
What is needed is a receiver that is asynchronous yet sensitive enough to sense signals from one chip to another chip in a multi-chip superconductive integrated circuit without an external clock. Therefore, it is an object of the present invention to provide such a receiver that allows chip to chip communication for multi-chip superconductive integrated circuits without loss of signal.
SUMMARY OF THE INVENTION
In accordance with the teachings of the present invention, a receiver for providing chip-to-chip communication in a superconductor integrated circuit is provided. The receiver includes a detector circuit for asynchronously receiving an input current, a splitter circuit receiving the input current from the detector circuit for generating a first signal, a delay circuit receiving the input current from the splitter circuit for generating a delayed signal and a register circuit receiving the first signal from the splitter circuit and the delayed signal from the delay circuit for producing a Single Flux Quantum (SFQ) pulse. The receiver provides an asynchronous chip-to-chip communication between a multi-chip superconductive integrated circuit having low input current without an external rf clock.
Additional objects, advantages, and features of the present invention will become apparent to those skilled in the art from the following discussion and the accompanying drawings and claims.


REFERENCES:
patent: 5598105 (1997-01-01), Kurosawa et al.
patent: 5963351 (1999-10-01), Kaplounenko et al.
patent: 02000252811 (2000-09-01), None
K.K. Likharev and V.K. Semenov, “RSFQ Logic/Memory Family: a New Josephson-Junction Technology for Sub-Terahertaz-Clock-Frequency Digital Systems”,IEEE Transactions on Applied Superconductivity, vol. 1, No. 1, Mar., 1991.

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