High sensitive data signal amplifying circuit

Details High sensitive data signal amplifying circuit High sensitive data signal amplifying circuit

2000-11-28

2003-02-11

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S207000, C365S208000

Reexamination Certificate

active

06519196

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
Priority is claimed from Republic of Korean Patent Application No. 99-53904 filed Nov. 30, 1999, which is incorporated in its entirety by reference.
FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device; and, more particularly, to a data signal amplifying circuit capable of amplifying data signals having a small differential voltage by employing two stage amplifying units at data signal outputs.
PRIOR ART OF THE INVENTION
In a semiconductor memory device, a sense amplifier is a major part for outputting data stored at a memory cell, which detects and amplifies data signals.
In the sense amplifier, there are required high sensitivity for detecting and amplifying data signals having a small differential voltage, high speed for transferring the data signals, low power consumption and small area within a semiconductor substrate. Particularly, the sensitivity and the speed of the sense amplifier are most important factors to improve performance of the semiconductor memory device.
The differential voltage applied to the sense amplifier through a bit line and a bit bar line coupled to the memory cell can be expressed as follows:
Δ
⁢
 
⁢
V
=
Vcc
/
2
1
+
C
B
/
C
C
where C
B
is bit line capacitance and C
C
is cell capacitance. To increase the input differential voltage, C
B
/C
C
should be made as small as possible and a power voltage VCC should be as high as possible.
However, as memory capability is increased, the length of the bit line is lengthened so that the bit line capacitance C
B
increases. And because the power voltage VCC is reduced as size of a transistor is reduced, the input differential voltage &Dgr;V decreases.
Accordingly, there is required a high sensitive amplifying circuit capable of detecting and amplifying the decreased input differential voltage.
As the amplifying circuit, a current mirror type sense amplifier or a latch type sense amplifier is frequently used.
FIG. 1
shows a conventional data signal amplifying circuit including the latch type sense amplifier.
Referring to
FIG. 1
, the conventional data signal amplifying circuit comprises a bit line amplifying unit
10
for amplifying data stored at a memory cell and load the amplified data on the bit line/bit bar line BIT/BITB, a column address selecting unit
20
for transferring the bit line/bit bar line BIT/BITB depending on a column address signal Yi, a data signal amplifying unit
30
for amplifying data signals LIO/LIOB transferred from the column address selecting unit
20
and a data signal transferring unit
40
for transferring output signals PD/PDB from the data signal amplifying unit
30
to an output buffer unit
50
.
The bit line amplifying unit
10
includes the latch type sense amplifier in which complementary metal oxide semiconductor (CMOS) transistors
11
,
12
constructed by PMOS transistors P
12
, P
13
and NMOS N
11
, N
12
are cross-coupled. And the latch type sense amplifier is controlled by a first enable signal RTOEB applied to the controlling PMOS transistor
11
coupled between sources of the PMOS transistors P
12
, P
13
and a power voltage VCC and a second enable signal SE applied to the controlling NMOS transistor N
13
coupled between sources of the NMOS transistors N
11
, N
12
and a ground voltage GND.
The latch type sense amplifying unit
10
amplifies and outputs the data stored at the memory cell when the first enable signal RTOEB is logic low and the second enable signal SE is logic high.
The column address selecting unit
20
includes NMOS transistors N
21
, N
22
. A gate of the NMOS transistors N
21
, N
22
is connected to the column address signal Yi. And NMOS transistors N
21
, N
22
are coupled to the bit line/bit bar line, respectively, for transferring the bit line/bit bar line signal BIT/BITB. When a column address is selected and the column address signal Yi is applied in logic high, the NMOS transistors N
21
, N
22
are turned on so that the bit line/bit bar line signal BIT/BITB are transferred to the data signal amplifying unit
30
.
The data signal amplifying unit
30
includes a latch type sense amplifier
32
for amplifying and outputting the output signals LIO/LIOB transferred from the column address selecting unit
20
and an equalizing unit
31
for controlling the output signals PD/PDB depending on a stand-by signal RSA_STB.
In the latch type sense amplifier
32
, sources of PMOS transistors P
34
, P
35
are coupled to the power voltage VCC. And a source of an NMOS transistor N
31
is coupled to an NMOS transistor N
33
having a gate connected to the output signal LIO of the column address selecting unit
20
, and a source of an NMOS transistor N
32
is coupled to NMOS transistors N
34
having a gate connected to the output signal LIOB of the column address selecting unit
20
. And the outputs PD/PDB of the latch type sense amplifier
32
are outputted from the drains of the PMOS transistors p
34
, p
35
. The output signals LIO/LIOB of the column address selecting unit
20
are respectively applied to the gates of the NMOS transistors N
33
, N
34
. And the sources of the NMOS transistors N
33
, N
34
are coupled to a drain of the NMOS transistor N
35
. A gate and a source of the NMOS transistor N
35
are respectively connected to the stand-by signal RSA_STB and to the ground voltage GND.
The equalizing unit
31
includes PMOS transistors P
31
, P
32
of which sources are coupled to the power voltage VCC and drains are coupled to the output PD/PDB of the latch type sense amplifier
32
, respectively, and PMOS transistor P
33
coupling the drains of the PMOS transistors P
31
, P
32
. To all the gates of the PMOS transistors P
31
, P
32
, P
33
, the stand-by signal RSA_STB is applied.
Therefore, while the stand-by signal RSA_STB is logic low, the PMOS transistors P
31
, P
32
, P
33
of the equalizing unit
31
are turned on and the NMOS transistor N
35
coupled to the ground voltage GND at bottom of the latch type sense amplifier
32
is turned off so that all the output signals PD/PDB of the data signal amplifying unit
30
outputs logic high signal, i.e., no amplifying performed. On the contrary, while the stand-by signal RSA_STB is logic high, the data signal amplifying unit
30
are amplified output signals PD/PDB.
The data signal transferring unit
40
includes inverters NOT
41
, NOT
42
for inverting the output signals PDB/PD of the data signal amplifying unit
30
and NMOS transistors N
41
, N
42
of which gates are connected to the outputs of the inverters NOT
41
, NOT
42
, respectively, and sources are coupled to the ground voltage GND. The data signal transferring unit
40
transfers the output signals PDB/PD of the data signal amplifying unit
30
to the output buffer unit
50
.
FIG. 2
is a signal waveform diagram showing data signal amplifying procedure performed by the data signal amplifying circuit. Referring to
FIG. 2
, the conventional data signal amplifying circuit amplifies differential voltage of the data signal LIO/LIOB transferred by the column address selecting unit
20
and transfers it to the output buffer unit
50
.
However, as memory devices becomes high integrated and capacitance of the bit lines BIT/BITB are increased, the differential voltage between the data signals applied to the amplifying circuit becomes too small to detect, which leads failure of the data signal amplifying circuit.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a data signal amplifying circuit capable of amplifying data signals having a small differential voltage by amplifying the data signals transferred from bit line amplifying unit in two stages.
In accordance with an aspect of the present invention, there is provided a high sensitive data signal amplifying circuit comprising: a bit line amplifying unit for amplifying data stored at a memory cell and loading the amplified data on one of a bit line and a bit bar line; a column address selecting unit for transferring an output signal of the bit line amplifying unit dependi

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