High-selectivity plasma-assisted etching of resist-masked layer

Details High-selectivity plasma-assisted etching of resist-masked layer High-selectivity plasma-assisted etching of resist-masked layer

1980-10-20

1982-06-08

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156646, 1566591, 204192EC, 204192E, 252 791, 427 40, 427 431, B44C 122, C03C 1500, C03C 2506

Patent

active

043337937

ABSTRACT:
In a VLSI device fabrication process, erosion of a patterned resist layer (16, 18) during dry etching of an underlying layer (14) can significantly limit the high-resolution patterning capabilities of the process. As described herein, a protective polymer layer (60, 62) is formed and maintained only on the resist material (16, 18) while the underlying layer (14) is being etched. High etch selectivities are thereby achieved. As a consequence, very thin resist layers can be utilized in the fabrication process and very-high-resolution patterning for VLSI devices is thereby made feasible.

REFERENCES:
patent: 3816196 (1974-06-01), La Combe
patent: 3940506 (1976-02-01), Heinecke
patent: 4226896 (1980-10-01), Coburn et al.
patent: 4244799 (1981-01-01), Fraser et al.
patent: 4275286 (1981-06-01), Hackett
The Bell System Technical Journal, vol. 58, No. 5, May-Jun. 1979, High Resolution Steep Profile Resist Patterns, by Moran et al., pp. 1027-1036.

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