Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-10-29
2002-05-07
Goudreau, George (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S713000, C438S714000, C438S723000, C438S724000, C438S701000, C438S725000, C438S739000, C438S740000, C430S005000
Reexamination Certificate
active
06383945
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the manufacture of semiconductor chips. More specifically, the present invention relates to a method of etching protective topside stack film to expose metal bonding pads.
BACKGROUND OF THE INVENTION
One of the final steps in manufacturing a semiconductor device involves etching large openings in a thick protective topside stack film to expose metal bonding pads for electrical connections to the outside world. This step is referred to as a pad etch.
FIGS. 1
a
and
1
b
illustrate a prior art pad etch. In
FIG. 1
a
a semiconductor device
10
comprises a device layer
23
under an interlayer dielectric
11
with an upper surface with a metal pad
12
. A thin titanium nitride (TiN) layer
14
covers an upper surface of the metal pad
12
. An oxide film
16
covers the upper surface of the substrate and thin titanium nitride layer
14
. A nitride film
18
covers the upper surface of the oxide film
16
. The oxide film
16
and the nitride film
18
make up a protective topside stack film. Various combinations of oxide film and nitride films may be used in the protective topside stack film. In the prior art a resist layer
20
is placed over the topside stack film and masked to provide an aperture
22
in the resist layer
20
over the metal pad
12
. The semiconductor device
10
is subjected to an anisotropic oxide plasma etch, which in the prior art is generally a fluorine based high power anisotropic oxide plasma etch.
FIG. 1
b
illustrates the semiconductor device
10
after it is undergone the anisotropic oxide plasma etch. The anisotropic plasma etch etches an aperture through the oxide film
16
, nitride film
18
, and titanium nitride layer
14
. An etch with straight vertical side walls is characteristic of an anisotropic oxide plasma etch.
The prior art anisotropic oxide plasma pad etches had a low throughput due to the thick oxide and nitride films. Long etch times in high power etching caused resist damage (burning and erosion). The prior art anisotropic oxide plasma pad etches had a low selectivity to resist of approximately 1:1 for nitride to resist and 2:1 for oxide to resist, as shown by the etching of the resist layer
20
between
FIGS. 1
a
and
1
b
The low selectivity to resist of the pad etch process requires the resist layer to be as thick as possible and the topside stack film to be as thin as possible. The thickness of the topside stack film is limited to about 2.5 microns or less in thickness due to the low selectivity to resist of the pad etch process.
It is desirable to etch topside stack films greater than 2.5 microns using a thin resist layer.
BRIEF SUMMARY OF THE INVENTION
It is an object of the invention to provide a pad etch process that is able to etch through a topside stack film that is greater than 2.5 microns.
It is another object of the invention to provide a pad etch process that has a faster throughput and less resist damage.
Accordingly, the foregoing objects are accomplished by etching a topside stack film with an isotropic etch that has a very good selectivity to resist.
Other features of the present invention are disclosed or apparent in the section entitled: “DETAILED DESCRIPTION OF THE INVENTION.”
BRIEF DESCRIPTION OF DRAWINGS
For a fuller understanding of the present invention, reference is made to the accompanying drawings wherein:
FIGS. 1
a
and
1
b
are cross sectional views device undergoing an anisotropic etch used in the prior art.
FIG. 2
is a cross sectional view of a semiconductor device used in the preferred embodiment of the invention.
FIG. 3
is a schematic view of a downstream plasma isotropic etching device used in the preferred embodiment of the invention.
FIG. 4
is a cross sectional view of the semiconductor device shown in
FIG. 2
after it has undergone isotropic etching.
FIG. 5
is a schematic view of an anisotropic etching device used in the preferred embodiment of the invention.
FIG. 6
is a cross sectional view of the semiconductor device shown in
FIG. 4
after it has undergone anisotropic etching.
FIG. 7
is a cross sectional view of a semiconductor device used in another embodiment of the invention.
FIG. 8
is a cross sectional view of the semiconductor device shown in
FIG. 7
after it has undergone isotropic etching.
Reference numbers refer to the same or equivalent parts of the present invention throughout the several Figures of the drawing.
REFERENCES:
patent: 4423547 (1984-01-01), Farrar et al.
patent: 5433823 (1995-07-01), Cain
patent: 5637904 (1997-06-01), Zettler
patent: 5824233 (1998-10-01), Zettler
patent: 5883001 (1999-03-01), Jin et al.
patent: 5960306 (1999-09-01), Hall et al.
patent: 6001538 (1999-12-01), Chen et al.
“Effect of Film Type On Isotropic Etch Activation Energy”; Proc.-Elect. Soc. (1998'); Abstract; Duton.
Holbrook Allison
Huang Jiahua
Shields Jeffrey A.
Goudreau George
LaRiviere Grubman & Payne, LLP
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