High selectivity mask oxide etching to suppress silicon pits

Details High selectivity mask oxide etching to suppress silicon pits High selectivity mask oxide etching to suppress silicon pits

1998-11-27

2001-04-24

Wilczewski, M. (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S720000, C438S738000, C438S952000

Reexamination Certificate

active

06221745

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of preventing silicon pits in the active region in the fabrication of integrated circuits.
(2) Description of the Prior Art
As device sizes shrink into the sub-micron and sub-half-micron regime, it has become necessary to use a combination of polysilicon and refractory metal suicides as the material for gate electrodes and interconnection lines because of their reduced resistivity. It is also essential to keep the active regions as free from defects as possible. Pitting of the silicon in the active areas can cause junction leakage and low yields.
FIG. 1
illustrates a partially completed integrated circuit device in which formed on a semiconductor substrate
10
. A gate oxide
14
is grown on the substrate and overlaid with a polysilicon layer
16
. Silicide layer
18
is deposited over the polysilicon layer and a tetraethoxysilane (TEOS) oxide layer
20
overlies the silicide layer as a hard mask. A barrier and antireflective coating (BARC) layer
22
is coated over the TEOS oxide layer
20
to underlay the photoresist mask
24
.
Pinhole
25
forms in the BARC layer due to spin speed. As the BARC and hard mask layers
22
and
20
are etched to form the hard mask, as shown by dotted lines in
FIG. 1
, the portion of the layers underlying the pinhole
25
etches faster than the other portions of the layers resulting in a pit
27
in the silicide layer
18
, as shown in FIG.
2
. This pit may penetrate about 300 Angstroms into the silicide layer. When the polysilicon and silicide layers
16
and
18
are patterned to form a gate electrode, as illustrated by the dotted lines in
FIG. 2
, a pit is formed in the silicon underlying the silicide pit
27
. Pitting of the silicon in the active areas can cause junction leakage and low yields.
Co-pending U.S. patent applications Ser. Nos. 09/004,188 to C. M. Yang et al and 09/004,190 to C. M. Yang et al, both filed on Jan. 8, 1998, teach different methods of preventing silicon pits in the active region by eliminating voids at the silicide/polysilicon interface. U.S. Pat. No. 5,710,076 to Dai et al teaches a two-step etching process in which the BARC and photoresist layers are etched using O
2
/CHF
3
/Ar, followed by an oxide etch using CHF
3
/CF
4
/Ar with a selectivity of oxide to BARC of 10:3. The use of CHF
3
and CF
4
as oxide etchants is disclosed in the book,
ULSI Technology
by C. Y. Chang and S. M. Sze, McGraw-Hill Company, NY, N.Y., C. 1997, pp. 353-354.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating polycide gate electrodes in the fabrication of integrated circuit devices.
A further object of the invention is to provide a method of fabricating polycide gates wherein silicon pits in the active region are avoided.
Yet another object of the invention is to provide a method of fabricating polycide gate electrodes wherein pinholes in a BARC layer do not significantly penetrate the silicide layer.
Yet another object is to provide a method of fabricating polycide gate electrodes wherein silicon pits in the active region are avoided by preventing pinholes in a BARC layer from penetrating significantly the silicide layer.
A still further object of the invention is to provide a method of fabricating polycide gate electrodes wherein silicon pits in the active region are avoided by using a two-step etch to prevent pinholes in a BARC layer from penetrating significantly the silicide layer.
Yet another object of the invention is to provide a method of fabricating polycide gate electrodes wherein silicon pits in the active region are avoided by using a two-step etch in which a BARC layer is first etched and then the hard mask layer is etched secondly to prevent pinholes in the BARC layer from penetrating significantly the silicide layer.
In accordance with the objects of this invention a method for fabricating polycide gate electrodes wherein silicon pits in the active region are avoided by using a two-step etch to prevent pinholes in a BARC layer from penetrating significantly the silicide layer is achieved. A layer of gate silicon oxide is grown over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate silicon oxide layer. A silicide layer is formed overlying the polysilicon layer. A hard mask layer is deposited overlying the silicide layer. An anti-reflective coating layer is formed overlying the hard mask layer. A photoresist mask is formed over the anti-reflective coating layer wherein a pinhole is formed in the surface of the anti-reflective coating layer not covered by the photoresist mask. First the anti-reflective coating layer is etched through using O
2
and N
2
gases where it is not covered by the photoresist mask to the hard mask layer. Secondly, the hard mask layer is etched through using CHF
3
, CF
4
, Ar, and N
2
gases where it is not covered by the photoresist mask to the silicide layer wherein the pinhole in the anti-reflective coating layer does not significantly penetrate the silicide layer. The silicide, polysilicon and gate silicon oxide layers are patterned where they are not covered by the hard mask wherein since the pinhole does not significantly penetrate the silicide layer, formation of silicon pits in the semiconductor substrate is prevented.


REFERENCES:
patent: 5468340 (1995-11-01), Gupta et al.
patent: 5710076 (1998-01-01), Dai et al.
patent: 5773199 (1998-06-01), Linliu et al.
patent: 5869403 (1999-02-01), Becker et al.
patent: 5924000 (1999-07-01), Linliu
patent: 5924001 (1999-07-01), Yang et al.
patent: 5935877 (1999-08-01), Autryve
C.Y. Chang et al.“VLSI Technology” McGraw-Hill Company, NY, NY, 1997, p 353-354.

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