Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-12-03
2002-12-17
Goudreau, George (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S714000, C438S717000, C438S724000, C438S736000, C438S687000, C430S005000
Reexamination Certificate
active
06495469
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor fabrication and more specifically to damascene etch methods.
BACKGROUND OF THE INVENTION
When simultaneously etching wide and relatively narrow trenches/vias, the microloading effect produces more etching in open areas (wide trenches/vias)than in narrow/dense areas. Thus, wider openings are generally etched deeper than narrow openings.
U.S. Pat. No. 6,211,092 B1 to Tang et al. describes a dual damascene etch process using a CHF/O
2
/Ar etch with anti-reflective coating (ARC) layers.
U.S. Pat. No. 5,843,847 to Pu et al. and U.S. Pat. No. 5,445,710 to Hori et al. each describe low-k material etches with CO/N/CHF and Ar etch chemistries.
U.S. Pat. No. 6,232,134 B1 to Farber et al. describes a method and apparatus for monitoring wafer characteristics and/or semiconductor processing consistency using wafer charge distribution measurements.
U.S. Pat. No. 6,087,266 to Abraham describes methods an apparatus for improving microloading while etching a substrate.
U.S. Pat. No. 5,930,677 to Zheng et al. describes a method for reducing microloading in an etchback of spin-on-glass or polymer.
SUMMARY OF THE INVENTION
Accordingly, it is an object of an embodiment of the present invention to provide an improved method of high selectivity, low etch depth micro-loading process for non middle stop layer damascene etching.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure having a low-k dielectric layer formed thereover is provided. A DARC layer is formed over the low-k dielectric layer. A patterned masking layer is formed over the DARC layer. Using the patterned masking layer as a mask, the DARC layer and the low-k dielectric layer are etched employing an CH
x
F
y
/O
2
/N
2
/Ar etch chemistry.
REFERENCES:
patent: 5445710 (1995-08-01), Hori et al.
patent: 5843847 (1998-12-01), Pu et al.
patent: 5930677 (1999-07-01), Zheng et al.
patent: 6087266 (2000-07-01), Abraham
patent: 6114259 (2000-09-01), Sukharev et al.
patent: 6211092 (2001-04-01), Tang et al.
patent: 6232134 (2001-05-01), Farber et al.
patent: 6294457 (2001-09-01), Liu
patent: 6376366 (2002-04-01), Lin et al.
Chao Li-Chih
Lin Li-Te S.
Yang Jiing-Feng
Ackerman Stephen B.
Goudreau George
Saile George O.
Stanton Stephen G.
Taiwan Semiconductor Manufacturing Company
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