Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-05-09
2004-05-18
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S062000, C345S063000, C345S066000, C345S067000, C345S068000, C345S204000, C345S208000, C315S169400
Reexamination Certificate
active
06738033
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a gas discharge panel display apparatus such as a plasma display panel and a drive method for the same, used in computers, televisions and the like.
RELATED ART
Recently, rising demand for the production of a high-quality large-screen television such as is required for high-definition television (HDTV) has led to the development of display panels aiming to fill this gap in various technological fields, including cathode ray tubes (CRTs), liquid crystal displays (LCDs) and plasma display panels (PDPs).
CRTs are in widespread use as television displays, and demonstrate excellent resolution and image quality. However, the depth and weight of CRTs increase with screen size, making them unsuited for large-screens of 40 inches or more. LCDs, meanwhile, have low power consumption and a low drive voltage, but the manufacture of a large-screen LCD is technically difficult.
Projection displays use a complicated optical system, requiring precise adjustment of the optical axis, which raises manufacturing costs. The optical system is also susceptible to optical distortion, causing a dramatic deterioration in picture quality and a worsening in spatial frequency resolution characteristics. Such problems make projection displays unsuitable as high-resolution displays.
In the case of PDPs however, large flat-panel screens can be realized, and products in the 50-inch range are already being developed.
PDPs can be broadly divided into two types: direct current (DC) and alternating current (AC). AC PDPs are suitable for large-screen use and so are at present the dominant type.
In a conventional AC PDP, a front substrate and a back substrate are placed in parallel with barrier ribs sandwiched between them. A discharge gas is enclosed in discharge spaces divided by the barrier ribs. Scan electrodes and sustain electrodes are placed in parallel on the front substrate, and covered by a dielectric layer of lead glass. Address electrodes, barrier ribs and a phosphor layer, formed of red, green and blue phosphors excited by ultraviolet light, are arranged on the back substrate.
To drive a PDP, a drive circuit applies pulses to electrodes to cause discharge to occur in the discharge gas which emits ultraviolet light. Phosphor particles (red, green and blue) in the phosphor layer receive the ultraviolet light and are excited, emitting visible light.
However, discharge cells in this kind of PDP are fundamentally only capable of two display states, ON and OFF. Thus, an address-display-period-separated (ADS) sub-field drive method in which one field is separated into a plurality of sub-fields and the ON and OFF states in each sub-field are combined to express a gray scale is performed for each of the colors red, green and blue.
Each sub-field is composed of a set-up period, an address period, and a discharge sustain period. In the set-up period, set-up is performed by applying pulse voltages to all of the scan electrodes. In the address period, pulse voltages are applied to selected address electrodes while pulse voltages are applied sequentially to the scan electrodes. This causes a wall charge to accumulate in the cells to be lit. In the discharge sustain period, pulse voltages are applied to the scan electrodes and the sustain electrodes, generating discharge. This sequence of operations causing an image to be displayed on the PDP is the ADS sub-field drive method.
The NTSC (National Television System Committee) standard for television images stipulates a rate of 60 field-images per second, so the time for one field is set at 16.7 ms.
Means for Resolving the Above Problems
Currently, PDPs used for televisions in the 40-42-inch range conforming to the NTSC standard (640×480 pixels, a cell pitch of 0.43 mm×1.29 mm, and individual cell area of 0.55 mm
2
) can achieve a panel efficiency of 1.2 lm/W and screen luminance of 400 cd/m
2
, as described in FLAT-PANEL DISPLAY 1997, part 5~1, p. 198. However, even higher luminance is desirable.
HDTV having a high resolution of up to 1920×1080 pixels is currently being introduced. It is therefore desirable for PDPs, as it is for other types of display panel, to be able to realize this kind of high-resolution display.
However, high-resolution PDPs have a large number of scan electrodes, producing a corresponding increase in the length of the address period. Here, if the length of each field and the time required for set-up in each case are uniform, an increase in the length of the address period limits the proportion of each field occupied by the discharge sustain period to a lower level.
The proportion of each field occupied by the discharge sustain period is accordingly reduced in higher-resolution PDPs. The panel luminance of a PDP is proportional to the relative length of the discharge sustain period, so that increases in resolution tend to reduce panel luminance.
Therefore, the necessity of improving panel luminance when realizing a high-resolution PDP becomes still higher.
Various techniques are utilized in the art to attempt to resolve these difficulties. These include a technique for increasing the luminous efficiency of cells, improving overall panel luminance, by a method for improving the luminous efficiency of the phosphor layer, and a technique for performing scanning during the address period using a dual scanning method so that the same number of scan lines can be covered in approximately half the time.
These techniques have had some effect in overcoming the above problems, but do not provide a satisfactory response to the demands of a PDP having both high-resolution and high luminance. Therefore, other techniques should ideally be used in combination with these techniques to solve the problem.
DISCLOSURE OF INVENTION
The object of the present invention is to provide a gas discharge panel display apparatus and a gas discharge panel drive method capable of realizing a high-resolution construction along with high luminance.
To achieve this object, a voltage is applied between scan and address electrode groups to perform set-up when a gas discharge panel is driven. The voltage waveform has four intervals. In a first interval, the voltage is raised in a short time (less than 10 &mgr;s) to a first voltage, wherein 100 V≦first voltage<starting voltage. Then, in a second interval, the voltage is raised to a second voltage no less than the starting voltage and with an absolute gradient smaller than that for the voltage rise in the first interval (no more than 9 V/&mgr;s). Next, in a third interval, the voltage is lowered in a short time (no more than 10 &mgr;s) from the second voltage to a third voltage no more than the starting voltage. Following this, in a fourth interval, the voltage is lowered still further (for 100 &mgr;s to 250 &mgr;s) with a gradient smaller than that for the voltage fall in the third interval. The time occupied by the whole voltage waveform should be no more than 360 &mgr;s.
If this kind of voltage waveform is used during set-up, a wall charge accumulates efficiently during the periods when the voltage rises and falls gently (i.e. the periods when the gradient for the voltage variation is no more than 9 V/&mgr;s). This means that a wall voltage near the level of the starting voltage can be applied during the set-up period.
Applying a wall voltage near the level of the starting voltage enables a wall charge to be accumulated properly and stable addressing to be performed, even if the pulses applied during the address period are short (no more than 1.5 &mgr;s).
Furthermore, the voltage variation from the first to third intervals is a short time (no more than 10 &mgr;s). This enables the total time for applying the set-up voltage to be restricted to no more than 360 &mgr;s. As a result the proportion of the driving time occupied by the set-up period (the proportion of one field occupied by the set-up period) is shortened.
The total time occupied by the set-up and address periods is thus shortened, allowing the time occupied by the discharge sustain period to be corres
Hibino Junichi
Higashino Hidetaka
Miyashita Kanako
Nagao Nobuaki
Ookawa Masafumi
Kovalick Vincent E.
Matsushita Electric - Industrial Co., Ltd.
Shalwala Bipin
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