Single-crystal – oriented-crystal – and epitaxy growth processes; – Processes of growth from liquid or supercritical state – Having pulling during growth
Reexamination Certificate
2001-12-06
2004-01-06
Hiteshew, Felisa (Department: 1765)
Single-crystal, oriented-crystal, and epitaxy growth processes;
Processes of growth from liquid or supercritical state
Having pulling during growth
C117S014000, C117S036000, C117S084000, C117S089000
Reexamination Certificate
active
06673147
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of producing a high-resistivity silicon wafer. More particularly, the present invention relates to a method of producing a high-resistivity silicon wafer which exhibits minimal change in resistivity upon heat treatment during device processing.
BACKGROUND OF THE INVENTION
High resistivity silicon wafers have conventionally been used for power devices such as high-voltage power devices and thyristors. More recently, C-MOS devices, Schottky barrier diodes, and other semiconductor devices for use in mobile communications have been developed which require the use of high-resistivity silicon wafers. The high-resistivity wafers tend to decrease the effects of parasitic capacitance among the devices of the wafer, allowing the devices to be more closely packed upon the surface of the wafer while, at the same time, reducing signal transmission loss among the devices.
High-resistivity wafers are generally defined as those silicon wafers with resistivity of 100 &OHgr;·cm or greater, and typically have resistivity of 1000 &OHgr;·cm or greater. The initial resistivity of a wafer is established during crystal growth by the precise addition of dopants to the molten polysilicon from which the silicon crystal is formed. By doping, the resistivity of the crystals can be controlled within close tolerances. However, the initial resistivity may be altered, desirably or undesirably, during subsequent processing of the wafer such that the final resistivity of the wafer may be very different from the resistivity directly after crystal growth.
In order to form more devices from a single wafer and therefore reduce the cost per device, larger wafers are generally preferred. As such, while high resistivity silicon wafers may be fabricated by a float zone technique, the limitations on size of the resulting wafers make the Czochralski (CZ) crystal growing method the desired fabrication technique. The CZ method allows wafers having diameters of 200 mm, 300 mm, 400 mm, or larger to be produced. In addition to the large wafer diameter, the CZ method also provides wafers with excellent planar resistivity distribution and lower cost. Good planar resistivity distribution means that the wafer has only minimal variations in resistivity along the plane which was perpendicular to the direction of pull of the crystal during crystal growth.
Unfortunately, there are some problems related to the presence of oxygen during the growth of high-resistivity silicon wafers in a CZ apparatus. During crystal growth within a CZ apparatus, oxygen from the quartz crucible tends to be introduced into the silicon crystal and is maintained in the interstitial spaces of the silicon crystal lattice. The interstitial oxygen atoms are normally electrically neutral, but the oxygen atoms tend to agglomerate as oxygen-containing thermal donors (OTDs), which become electron donors when subjected to heat in the range of 350° C. to 500° C. Thus, the resistivity of the wafer may be unfavorably decreased by a relatively mild heating due to the contribution of electrons from the OTDs residing in the wafer. The decrease in resistivity due to the oxygen is especially problematic considering that temperatures in the range of 350° C. to 500° C. are commonly encountered during process steps subsequent to wafer fabrication, such as during device fabrication.
The elimination of oxygen from the silicon lattice is not a complete solution to the problem of resistivity variation within a silicon wafer. The presence of oxygen within the silicon crystal causes oxygen precipitate bulk defects to form within the crystal. Though large numbers of bulk defects are not desired, small numbers of bulk defects contribute to a gettering effect within the crystal. By gettering, the defects within the crystal act to trap mobile ionic contamination and to prevent the contamination from traveling to the surface of the wafer. The gettering is necessary to protect the devices on the surface of the wafer from interference from the contaminants.
As described in European Patent Office publication EP 1087041 A1, incorporated herein by reference, there is known a method of producing a high-resistivity wafer having a high gettering effect while preventing the reduction of resistivity due to electrons being donated from OTDs upon subsequent heating cycles of the wafer. The method includes first producing a single crystal ingot having a resistivity of 100 &OHgr;·cm or greater and an initial interstitial oxygen concentration of 10 to 25 parts per million atomic (ppma) by a CZ method. Interstitial oxygen is then precipitated with a gettering heat treatment step until the residual interstitial oxygen concentration in the wafer becomes about 8 ppma or less. The precipitated oxygen does not have the ability to donate electrons like the OTDs formed from interstitial oxygen so subsequent heat treating processes do not result in a reduction in resistivity.
The use of the gettering heat treatment step is capable of reducing the oxygen content of a 100 &OHgr;·cm wafer from 10 to 25 ppma to 8 ppma or less while generating or maintaining a bulk defect density of 1×10
8
to 2×10
10
defects/cm
3
. This number of defects is sufficient to provide gettering to the wafer in order to trap contaminants and prevent the contaminants from moving to the surface of the wafer. The wafer described above will maintain high resistivity through subsequent low temperature heat treatments, such as device heat treatments at 350° C. to 500° C., while maintaining sufficient gettering effect.
The main drawback with the above described gettering heat treatment, however, is the process time required to precipitate the oxygen within the wafer. Typically, for example, the heat treatment process may require a first heating step of 800° C. for 4 hours, a second heat treating step of 1000° C. for 10 hours, and a third heat treatment step of 1050° C. for 6 hours. The extended process time required to maintain the wafer at temperature until the oxygen content of the wafer is reduced from 10 to 25 ppma to 8 ppma or less lowers the overall efficiency of the wafer making process, both in terms of time and in terms of power requirements.
What is needed is a method of improving the speed and quality of the precipitation of interstitial oxygen during the gettering heat treatment of a high-resistivity wafer in which oxygen content of the wafer is reduced from 10 ppma or greater to 8 ppma or less and in which the bulk defect density is 1×10
8
to 2×10
10
defects/cm
3
.
SUMMARY OF THE INVENTION
The invention is a method of treating a high-resistivity silicon wafer containing interstitial oxygen in such a way that the oxygen is largely precipitated, which prevents the oxygen from acting as an electron donor and prevents the resistivity of the wafer from diminishing. Specific dopants are used to aid precipitation of the oxygen and to minimize the thermal energy required to cause precipitation.
The improved method of obtaining a wafer exhibiting high resistivity and high gettering effect while preventing the reduction of resistivity due to the generation of oxygen donors is provided by: a) using the CZ method to grow a silicon single crystal ingot having a resistivity of 100 &OHgr;·cm or more and an initial interstitial oxygen concentration of 10 to 40 ppma while doping the crystal with electrically inactive impurities which enhance oxygen precipitation during a high temperature annealing process, b) processing the ingot into a wafer, and c) subjecting the wafer to an oxygen precipitation heat treatment whereby the residual interstitial oxygen content in the wafer is reduced to about 8 ppma or less. Exemplary electrically inactive impurities are nitrogen, carbon, or tin.
The resulting wafer has high resistivity, increased gettering ability, and is resistant to slip dislocations. Precipitation of the interstitial oxygen content prevents the oxygen constituents from becoming electrically active electron donors upon subsequent heat treatments of the si
Kononchuk Oleg V.
Koveshnikov Sergei V.
Radzimski Zbigniew J.
Weaver Neil A.
Alston & Bird LLP
Hiteshew Felisa
SEH America Inc.
LandOfFree
High resistivity silicon wafer having electrically inactive... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High resistivity silicon wafer having electrically inactive..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High resistivity silicon wafer having electrically inactive... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3257014