Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-04-17
2007-04-17
Baker, Stephen M. (Department: 2133)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S763000, C714S767000, C714S772000
Reexamination Certificate
active
10723055
ABSTRACT:
A memory subsystem comprising: a command register in operable communication with a plurality of memory devices via a plurality of command buses. The plurality of memory devices is arranged into symbol slices and each symbol slice is configured to be part of a single error correction code packet. Each command bus of the plurality of command buses is configured to interface between the command register and each memory device in a particular symbol slice. A method of command bus redundancy comprising: configuring a plurality of memory devices into symbol slices, each symbol slice configured to be part of a single error correction code packet; establishing a plurality of command buses, each command bus configured to interface with each memory device in a particular symbol slice; and configuring a command register with sufficient command bus drivers to support each command bus of the plurality of command buses.
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Deegan John M.
Gower Kevin Charles
Baker Stephen M.
Cantor & Colburn LLP
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