Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2008-04-29
2008-04-29
Baker, Stephen M. (Department: 2112)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S054000, C714S057000
Reexamination Certificate
active
11406719
ABSTRACT:
A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.
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Gower Kevin C.
Hazelzet Bruce
Kellogg Mark W.
Perhnan David J.
Augspurger Lynn L.
Baker Stephen M.
Cantor & Colburn LLP
International Business Machines - Corporation
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