Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-09-05
2006-09-05
Ngô, Ngân V. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S318000, C257S390000, C257SE27016, C257SE27071
Reexamination Certificate
active
07102188
ABSTRACT:
An EEPROM cell that combines a FET transistor and a capacitor. The transistor has a well that is shared by potentially all of the EEPROM cells in the array thereby reducing size. A gate terminal is formed over the well. Source and drain terminals are formed in the well. The well is isolated from the gate terminal using a dielectric layer. A first terminal of the capacitor is connected to the gate terminal using a dielectric layer. A first terminal of the capacitor is connected to the gate terminal, and may be oppositely doped from the gate terminal to improve retention. The second terminal is formed by a second well that is underneath the first terminal and isolated from the first terminal. The capacitance may be increased without area increase by forming a metal layer over the first terminal and separated from the first terminal by a thick dielectric layer, and connected to the second well via a conductive via.
REFERENCES:
patent: 4924278 (1990-05-01), Logie
patent: 5465231 (1995-11-01), Ohsaki
patent: 5929478 (1999-07-01), Parris et al.
patent: 6100560 (2000-08-01), Lovett
patent: 6141238 (2000-10-01), Forbes et al.
patent: 2004/0070020 (2004-04-01), Fujiwara et al.
patent: 2004/0071008 (2004-04-01), Chen et al.
patent: 2004/0212005 (2004-10-01), Lojek
An Experimental 5-V-Only 256-kbit CMOS EEPROM with a High-Performance Single -Polysilicon Cell Jun-Ichi Miyamoto, Jun-Ichi Tsujimoto, Naohiro Matsukawa, Shigeru Morita, Kazuyoshi Shinada, Hiroshi Nozawa, & Tetsuya Iizuka IEEE Journal of Solid—State Circuits, vol. SC-21, No. 5, Oct. 1986 p. 852-860.
“Thickness Scaling Limitation Factors of ONO Interpoly Dielectric for Nonvolatile Memory Devices” Seiichi Mori, Yoshiko Yamaguchi Araki, Muneharu Sato, Hisataka Meguro, Hiroaki Tsunoda, Eiji Kamiya, Kuniyoshi Yoshi Yoshikawa, Norihisa Arai and Eiji Sakagami IEEE Transactions on Electron Devices, vol. 43, No. 1, Jan. 1996 p. 47-53.
“Theoretical and Experimental Investigation of Si Nanocrystal Memory Device With HfO2 High-k Tunneling Dielectric” Jong Jin Lee, Xuguang Wang, Weiping Bai, Nan Lu, and Dim-Lee Kwong IEEE Transactions on Electron Devices, vol. 50, No. 10, Oct. 2003 p. 2067-2072.
“Impact of Crystal Size and Tunnel Dielectric on Semiconductor Nanocrystal Memory Performance” Min She and Tsu-Jae King IEEE Transactions on Electron Devices, vol. 50, No. 9, Sep. 2003 p. 1934-1940.
“Twin MONOS Cell with Dual Control Gates” Yutaka Hayashi, Seiki Ogura, Tomoya Saito, Tomoko Ogura 2000 Symposium on VLSI Technology Digest of Tecnical Papers 2000 IEEE.
“A Flash EEPROM Cell with Self-Aligned Trench Transistor & Isolation Structure” Ken-ichiro Nakagawa, Kazuyoshi Yoshida, Shuichi Masuda, Akira Yoshino and Isami Sakai 2000 Symposium on VLSI Technology Digest of Tecnical Papers 2000 IEEE.
“Reliably Implications in Advanced Embedded Two-Transistor-Fowler-Nordheim-NOR Flash Memory Devices” A. Scarpa, G. Tao, J. Dijkstra , F.G. Kuper Solid-State Electronics p. 1765-1773.
Cacharelis Philip John
Gassot Pierre André Claude
Scott Greg
Yao Thierry Coffi Hervé
AMI Semiconductor Inc.
Ngo Ngan V.
Workman Nydegger
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