High-reliability damascene interconnect formation for semiconduc

Details High-reliability damascene interconnect formation for semiconduc High-reliability damascene interconnect formation for semiconduc

1999-03-10

2000-12-05

Clark, Sheila V.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257251, 257622, H01L 2348, H01L 2352, H01L 2940

Patent

active

061570818

ABSTRACT:
A high-reliability damascene interconnect structure and a method for forming the same are provided. An interlevel dielectric is formed over a semiconductor topography, and trenches for interconnects and/or vias are formed in the interlevel dielectric. A trench liner may then be deposited, followed by deposition of a low-resistance metal such as copper. The low-resistance metal deposition is preferably stopped before the trenches are entirely filled. Portions of the metal and trench liner external to the trenches are subsequently removed, such that low-resistance metal interconnect portions are formed. A high-melting-point metal, such as tungsten, is deposited over upper surfaces of the interconnect portions and interlevel dielectric. Portions of the high-melting-point metal are removed to form interconnects having a low-resistance metal lower portion and a high-melting-point metal upper portion. In one embodiment, the extrusion-prone lowresistance metal is removed from the vicinity of a ready extrusion path between the interlevel dielectric and an overlying dielectric. In another embodiment, the overlying metal is believed to prevent extrusion of the low-resistance metal by bonding with the low-resistance metal and by altering the electric field distribution between adjacent interconnects.

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Steigerwald et al., Chemical Mechanical Planarization of Microelectronic Materials, John Wiley & Sons 1997, pp. 188-189 and 206-207.

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