High Q gyrator structures

Details High Q gyrator structures High Q gyrator structures

2000-11-30

2002-12-03

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06490706

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a filter circuit consisting of at least one filter stage in which amplifier-like circuits such as integrators and/or gyrators are employed to emulate the impedance of inductors. The invention also relates to a method for making (designing) such filter circuit.
The invention in particular addresses the problem how complex (higher order) filters can be designed such that the actual filter characteristics obtained in the practically realized filter circuit coincide with the theoretically designed filter characteristics. The invention also addresses the problem how such complex (e.g. higher order) filters can be designed such that they are stable.
BACKGROUND OF THE INVENTION
As shown in
FIG. 1
, typically a filter circuit consists of a plurality of filter stages FST
1
. . . FSTi wherein the first filter stage FST
1
is driven by a source, e.g. a current source CS and a source impedance SI, and the output of the last filter stage FSTi is terminated with an output impedance OI. As is well known to the skilled person the filter transfer function is essentially a polynomial consisting of a plurality of poles and zeros in the complex plane. Depending as to whether the individual filter stages FSTi are a filter stage of first order or higher order, a desired filter function and thus a desired filter characteristic can be obtained.
Hereinafter, it is assumed that each filter stage FSTi consists of a single transistor or gyrator. However, of course the invention is not restricted to each filter stage being of the said types but also higher order filter stages may be used.
Depending on the desired filter transfer function, each filter stage is realized by coils, resistors and capacitors. For example, on-chip filters are normally restricted to resistor/capacitor filter stages, except at very high frequencies where on-chip coils of a few nH may be employed. In such passive filter realizations (i.e. no active circuitry is employed in the filter stages FSTi) it therefore depends on how accurate or whether at all coils (more particular the coil impedance) can be realized by a passive coil construction.
As is also well known to the skilled person in the art of filter design, active on-chip filters are often used to circumvent the coil restrictions in passive filter circuits. In such active filters amplifier-like circuitry is used to emulate the impedance of the inductors. That is, the coils are replaced by an active circuit. For continuous-time filters such amplifier-like circuits typically consist of integrators or gyrators and for discrete-time circuits (digital filters) integrators are used for emulating the coils impedance.
Continuous-time filters implemented with integrators typically employ such elements in loops and these loops. Two integrators in a loop actually form a gyrator. If the forward and backward integrators have the same gain characteristics they form a passive gyrator and if they do not have the same gain characteristics they form an active (or asymmetric) gyrator.
FIG. 2
shows a typical block diagram of a gyrator and its equivalent circuit diagram. The input voltage V
1
and the output voltage V
2
are linked via the gyration constant g
m
* as I
1
=−g
m
*V
2
and I
2
=g
m
*V
1
. Thus, the gyrator shown in
FIG. 2
consists of a positive transconductance g
m
* and a negative transconductance −g
m
*.
FIG. 3
shows a typical realization of the gyrator in
FIG. 2
employing at least one common mode feedback section CMIi, CMOi and a gyrator core section GCi. As shown in
FIG. 3
, the negative transconductance −g
m
* is typically formed by employing differential signals and crossing one pair of wires. That is, the gyrator core section GCi comprises four inverters GI
1
i
-GI
4
i
mutually connected in a loop configuration between a pair of input terminals i_
1
; i_
2
and a pair of output terminals o_
1
; o_
2
. The common mode feedback section CMIi, CMOi is connected between the pair of input terminals and/or the pair of output terminals and comprises two series connections respectively formed by an inverter CMI
1
, CMO
1
and a short-circuited inverter CMI
2
, CMO
2
connected antiparallely between said input terminals or said output terminals. It should be noted that one of the input or output common mode feedback sections CMIi, CMOi is sufficient for realizing the positive transconductance g
m
* and that one gyrator core section GCi is sufficient for realizing the negative transconductance −g
m
.
However, independent as to how the actual inverters are realized (by MOS, CMOS, BiCMOS or bipolar transistors), the crossing of the wires results in a loop through the four inverters GI
1
i
, GI
2
i
, GI
3
i
, GI
4
i
.
FIG. 4
shows the realization of the inverters in
FIG. 3
using two CMOS transistors T
1
(e.g. NMOS) and T
2
(e.g. PMOS) whose drains D and gates G are connected with the respective sources connected to ground. Similarly, the short-sectioned inverters would correspond to the circuit configuration shown in
FIG. 4
with the input In and the output Out connected together.
Furthermore, gyrators realized by differential amplifier circuitry are possible, as shown in
FIGS. 5
a
,
5
b
.
FIG. 5
a
shows on the left-hand side the symbol for a transconductor realized by a differential amplifier and on right-hand side the inverter solution for such a differential type amplifier in CMOS technology is shown. Two inverters I
1
, I
2
(e.g. having a circuit configuration as shown in
FIG. 4
) are respectively connected to a first and second current source CS
1
, CS
2
which are biased by bias voltages bias
1
, bias
2
.
FIG. 5
b
shows the gyrator core section GCi of
FIG. 3
using a differential transconductor configuration as in
FIG. 5
a
. As shown on the left-hand side in
FIG. 5
b
two differential transconductors DA
1
, DA
2
are provided in a feedback loop and therefore, using the circuit configuration in
FIG. 5
a
, this leads to a structure similar to that shown in
FIG. 3
, namely loop-like circuits in the gyrator core section GCi.
In
FIG. 5
b
the circuit configuration of
FIG. 5
a
is contained twice leading to two first current sources CS
1
, CS
12
and to second current sources CS
21
, CS
22
, to first inverters I
11
, I
12
and to second inverters I
21
, I
22
.
It should be noted that any gyrator configuration as shown in
FIGS. 3
,
4
,
5
may be used for the filter circuit according to the invention as will be described below. That is, the present invention is not restricted to any particular gyrator constructions. However, any gyrator construction would lead to the loop-like circuit of the gyrator core section GCi as shown in FIG.
3
. The only difference is that for the differential amplifier gyrator shown in
FIG. 5
b
no common mode feedback is needed because in the differential transconductor a high CMRR (Common Mode Rejection Ratio) exists.
As explained above, the loop-like configuration of the gyrator leads to a stability problem and the stability analysis of the gyrator- and integrator-based filters is the same since the integrators are parts of gyrator loops. An analysis of the gyrators is thus valid for the integrator configuration as well.
DESCRIPTION OF THE PRIOR ART
The stability of filter circuits comprising a gyrator construction as shown in
FIG. 3
has been studied by B. Nauta: “A CMOS transconductance-C filter technique for very high frequencies in IEEE Journal of Solid-State Circuits, SC-27, pages 142-153, February 1992”. In this prior art document the stability of the circuit in
FIG. 3
(hereinafter called the Nauta cell) was conducted by assuming a MOS or CMOS transistor realization of the integrators in FIG.
3
. As is well known to the skilled person in the field of transistor technology, each MOS or CMOS transistor has a channel region of a particular dimension and the time needed for transporting carriers through this channel (between the source and drain) will influence the switching properties of the CMOS or MOS transistor.
In a PhD thesis which

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