High priority guard transfer for execution control of...

Details High priority guard transfer for execution control of... High priority guard transfer for execution control of...

2005-01-07

2009-02-24

Huisman, David J (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Processing control for data transfer

Reexamination Certificate

active

07496737

ABSTRACT:
A method of transferring guard values and a computer system, such as a processor for digital signal processing, including a parallel set of execution units that utilizes the method. A master set of guard indicators is held in association with one of the execution units. If other execution units require the guard values for particular guard indicators, a sendguard instruction is issued to the execution unit holding the master guard values. The sendguard instructions are held in a separate queue from the main instructions intended for that execution unit. Circuitry is provided in the execution unit to avoid stalling in the dispatch of sendguard instructions even in the context of earlier guard modifying instructions.

REFERENCES:
patent: 5301340 (1994-04-01), Cook
patent: 5651125 (1997-07-01), Witt et al.
patent: 5748936 (1998-05-01), Karp et al.
patent: 5859999 (1999-01-01), Morris et al.
patent: 5889984 (1999-03-01), Mills
patent: 5974537 (1999-10-01), Mehra
patent: 6041399 (2000-03-01), Terada et al.
patent: 6119221 (2000-09-01), Zaiki et al.
patent: 6216215 (2001-04-01), Palanca et al.
patent: 6374346 (2002-04-01), Seshan et al.
patent: 6393026 (2002-05-01), Irwin
patent: 6452857 (2002-09-01), Alofs et al.
patent: 6553478 (2003-04-01), Grossier
patent: 6678818 (2004-01-01), Cofler et al.
patent: 6701425 (2004-03-01), Dabbagh et al.
patent: 6711668 (2004-03-01), Wojcieszak et al.
patent: 6718452 (2004-04-01), Wojcieszak et al.
patent: 6725357 (2004-04-01), Cousin
patent: 6725365 (2004-04-01), Cofler et al.
patent: 6732276 (2004-05-01), Cofler et al.
patent: 6742131 (2004-05-01), Wojcieszak et al.
patent: 6769049 (2004-07-01), Bernard et al.
patent: 6807626 (2004-10-01), Cofler et al.
patent: 6854049 (2005-02-01), Cofler
patent: 0 403 014 (1990-12-01), None
patent: 0 490 524 (1992-06-01), None
patent: 1 050 805 (2000-11-01), None
Hennessy and Patterson, “Computer Architecture—A Quantitative Approach, 2nd Edition,” 1996, p. 136.
Intel Corporation, “IA-64 Application Developer's Guide,” May 1999, p. 11-13.
“Condition Register Coherency Look-Ahead” Research Disclosure, Kenneth Mason Publications, Hampshire, GB, No. 348, Apr. 1,k 1993, p. 243.
Labrousse J. et al. “Create-Life: A Modular Design Approach For High Performance ASIC's” Computer Society International Conference (COMPCON, Spring Meeting, Los Alamitos, Feb. 26-Mar. 2, 1990, No. CONF. 35, Feb. 26, 1990, pp. 427-433, XP000146217, Institute of Electrical and Electronics Engineers ISBN: 0-8186-2028-5.
Hennessy and Patterson, Computer Architecture—A Quantitative Approach, 2ndEdition, 1996, pp. 147-150.
Intel Corporation, “1A-64 Application Developer's Architecture Guide”, May 1999, pp. 3-3, 4, 14, 4-10, 7-3, 8, 19, 41, 127, 166.

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