Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-12-13
2005-12-13
Booth, Richard A. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S644000, C438S653000, C438S649000
Reexamination Certificate
active
06974773
ABSTRACT:
According to one embodiment of the invention, a high pressure anneal is utilized to form titanium silicide at the bottom of a contact hole, at a pressure of at least approximately 1.1 atmospheres, from a reaction between deposited titanium and underlying silicon. When such high pressures are used, temperatures of less than approximately 700 degrees Celsius are utilized. According to another embodiment of the invention, a conductive plug fill material is deposited within a contact hole such that the plug structure is relatively free of voids. Either during deposition of the conductive plug fill material or after such deposition, the conductive plug fill material is subjected to a high pressure force-fill, at a pressure of at least approximately 1.1 atmospheres. When such high pressures are used, temperatures of less than approximately 700 degrees Celsius are utilized for the force-fill. Aluminum can be used for the conductive plug fill material when using this embodiment of the invention. In further embodiments, dielectrics deposited between conductive layers are reflowed at high pressure and low temperature. Still further, multiple metalized layers are connected by vias filled with conductive material using high pressure and low temperature.
REFERENCES:
patent: 4420503 (1983-12-01), Leung et al.
patent: 4845055 (1989-07-01), Ogata
patent: 5043300 (1991-08-01), Nulman
patent: 5135608 (1992-08-01), Okutani
patent: 5147820 (1992-09-01), Chittipeddi et al.
patent: 5250467 (1993-10-01), Somekh et al.
patent: 5356835 (1994-10-01), Somekh
patent: 5434044 (1995-07-01), Nulman et al.
patent: 5502334 (1996-03-01), Shinohara
patent: 5527561 (1996-06-01), Dobson
patent: 5534461 (1996-07-01), Kuwajima
patent: 5679585 (1997-10-01), Gardner et al.
patent: 5783471 (1998-07-01), Chu
patent: 5851581 (1998-12-01), Zenke
patent: 5891805 (1999-04-01), Cheng et al.
patent: 5218906 (1995-06-01), None
Wolf, “Silicon Processing for the VLSI Era vol. 2: Process Integration”, Lattice Press, 1990, pp. 132-133.
Mizobuchi, et al., ““Application of Force fill A1-plug technology to 64 MB DRAM and 0.35 micron logic””,1995 Sympsoim on VLSI Technology, Digest of Technical Papers, abstract only, (1995).
Thakur Randhir P. S.
Zahurak John K.
Booth Richard A.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
LandOfFree
High pressure anneals of integrated circuit structures does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High pressure anneals of integrated circuit structures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High pressure anneals of integrated circuit structures will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3478355