Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1997-01-28
2001-01-16
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S683000, C438S909000
Reexamination Certificate
active
06174806
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to methods for fabricating semiconductor integrated circuits, and in particular, to forming contacts to various areas of such integrated circuits using high pressure annealing methods.
BACKGROUND OF THE INVENTION
Semiconductor integrated circuits (ICs) contain individual devices, which are typically operatively coupled together using metal line interconnects and various contacts. In most applications, the metal lines are formed on a different level than the devices, separated by an intermetal dielectric, such as silicon oxide or borophosphosilicate glass (BPSG). The most commonly used metal lines are aluminum, tungsten, copper, and combinations of the materials with refractory metals and silicon. Interconnects used to electrically couple devices and metal lines are formed between the individual devices and the metal lines. A typical interconnect is composed of a contact hole (i.e. opening) formed in an intermetal dielectric layer over an active device region. The contact hole is filled with a metal, such as aluminum or tungsten. Aluminum is preferred as an interconnect metal due to its high conductivity. Aluminum exhibits relatively low resistivity as compared to tungsten and, furthermore, is highly compatible with silicon oxide and other low temperature oxides, which are often used as the insulative material surrounding a contact hole. Furthermore, when metal lines are used, which are composed of aluminum, compatibility between the metal lines and the aluminum interconnect materials is optimized.
Interconnects often further contain a diffusion barrier layer sandwiched between the interconnect metal and the active device region at the bottom of the contact hole. Such layers prevent intermixing of the metal and material from the active device region, such as silicon, extending the life of the device. Passive titanium nitride diffusion barrier layers are the most common diffusion barrier layers.
Diffusion barrier layers are typically formed over a refractory metal silicide layer. Titanium silicide is the most commonly used refractory metal silicide due to its relatively low resistivity. The use of titanium silicide between titanium nitride and the active device region is preferred due to its intermediate crystallographic characteristics between those of silicon and titanium nitride, preventing increased resistivity resulting from a contact solely between silicon and titanium nitride. Silicon and titanium nitride have very different crystallographic characteristics. However, as aspect ratios (i.e. ratio of height to width of the contact hole) of typical contact holes increase to meet demands for high density ICs, uniform formation of titanium silicide at bottoms of contact holes is becoming more important, yet more difficult to obtain. Ideally, interconnects will exhibit zero impedance to current flow. However, interconnects typically exhibit near linear characteristics at best. An ohmic interconnect (i.e. one which exhibits linear current v. voltage characteristics and low resistance to current flow), provides optimum electrical performance. One way in which an interconnect is made more ohmic is by maintaining layers of uniform thickness and grain structure within a contact, such that there are not variations across the interconnect.
Furthermore, as ICs are scaled down in size, maintaining a minimal thermal budget during IC fabrication is also becoming more important. A thermal budget for fabricating an IC is the maximum combination of thermal steps and length of time during such thermal steps that an IC can withstand before its electrical characteristics are potentially degraded. For example, as ICs are scaled down in size, junction depths are becoming shallower. One of the problems associated with long thermal steps is dopant migration into undesired regions. Such shallow junctions are more easily degraded by long thermal steps due to dopant migration.
Of primary concern in depositing metal into a contact hole is obtaining adequate step coverage of the contact hole. This is particularly a problem when the contact holes have high aspect ratios, as seen more often as IC densities increase. To mitigate this problem, chemical vapor deposition (CVD) is used to deposit the metal instead of physical vapor deposition (PVD). CVD is more apt to adequately fill high-aspect ratio contact holes than PVD. However, to date, CVD aluminum exhibits rough, nonconformal layers on complex topographies, such as high aspect ratio contact holes, prior to surface modification. This is undesirable because voids often develop within a contact, due to the roughness of the CVD aluminum. Such voids severely increase the resistivity of an interconnect and degrade device performance by not providing uniform electrical connection across an interconnect. While high temperature steps are able to reflow metal within a contact hole after its deposition, they are undesirable because they increase the thermal budget as previously mentioned.
There is a need for a method for filling contact holes with aluminum or other similar materials, where the resulting contact hole is relatively free of voids. There is a further need for a method for forming titanium silicide effectively and uniformly on the bottom of contact holes, such that a minimal amount of thermal budget is consumed. Still further needs exist for filling holes such as vias connecting multiple metallic layers and for forming dielectric layers between capacitors to ensure that they are relatively free of voids.
SUMMARY OF THE INVENTION
The present invention teaches a method for forming contacts and/or conditioning the contacts to various areas of integrated circuits. In particular, this invention is advantageously utilized in contact holes having an aspect ratio of at least 2. Problems in obtaining adequate step coverage and uniformity of electrical connection in such contacts are overcome by use of the present invention. The same problems are also overcome for forming contacts between multiple layers of metalization, and in forming dielectrics between rough capacitor plates. This is accomplished while maintaining a low thermal budget.
In one embodiment, a high pressure anneal is utilized to form titanium silicide at the bottom of a contact hole. Titanium is first deposited on the bottom of a contact hole, which comprises silicon. Then, a titanium nitride layer is deposited on the titanium layer for a diffusion barrier layer. A high pressure anneal, at a pressure of significantly greater than one atmosphere (i.e. at least approximately 1.1 atmospheres) forms titanium silicide on the bottom of the contact hole from a reaction between the deposited titanium and underlying silicon. When such high pressures are used, temperatures of less than approximately 700 degrees Celsius are utilized, advantageously conserving thermal budget of a fabrication process. Depending on the type of refractory metals used, a preferred temperature range of 500 to 750 degrees Celsius and a pressure of 1.1 to 700 atmospheres is used. Furthermore, titanium silicide layers formed according to this embodiment of the invention have a more uniform thickness and more homogenous crystallographic structure. Thus, titanium silicide formed according to this invention provides a lower resistivity and more uniform ohmic interconnect structure.
In a further embodiment of the invention, the titanium nitride layer is omitted from the fabrication sequence. Then, the high pressure anneal occurs in a nitrogen-containing ambient to form a titanium nitride layer on the underlying titanium simultaneously with forming titanium silicide.
According to another embodiment of the invention, a conductive plug fill material is deposited within a contact or via hole such that the plug structure is relatively free of voids. Either during deposition of the conductive plug fill material or after such deposition, the conductive plug fill material is subjected to a high pressure force-fill. A pressure of at least approximately 1.1 atmospheres is used to adequately f
Thakur Randhir P. S.
Zahurak John K.
Booth Richard
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
LandOfFree
High pressure anneals of integrated circuit structures does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High pressure anneals of integrated circuit structures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High pressure anneals of integrated circuit structures will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2467901