High performance tiling for RRAM memory

Details High performance tiling for RRAM memory High performance tiling for RRAM memory

2005-10-24

2010-06-15

Verbrugge, Kevin (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

Reexamination Certificate

active

07739471

ABSTRACT:
A method of configuring a random access memory matrix containing partially configured memories in the matrix. The method includes the steps of independently calculating a memory enable signal and a configuration signal for a partially configured memory in each memory tile of the memory matrix. Memory tiles not supported by a memory compiler are determined. A memory wrapper is provided for each tile not supported by the memory compiler. An address controller is inserted in the memory matrix for each tile in a group of tiles. Output signals from each memory location in a memory group having a common group index are combined into a single output signal. A first stripe of memory tiles containing non-configured memory having a first width is selected. A second strip of memory tiles containing configured memory having a second width is also selected.

REFERENCES:
patent: 7219325 (2007-05-01), Lysaght

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