Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-08-04
2010-12-07
Garber, Charles D (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257SE21540, C257SE21545
Reexamination Certificate
active
07847358
ABSTRACT:
A semiconductor structure formed on a substrate and process for preventing oxidation induced stress in a determined portion of the substrate. The structure includes an n-FET device and a p-FET device, and a shallow trench isolation having at least one overhang is selectively configured to prevent oxidation induced stress in a determined portion of the substrate. The at least one overhang is selectively configured to prevent oxidation induced stress in at least one of a direction parallel to and a direction transverse to a direction of a current flow. For the n-FET device, the at least one overhang is selectively arranged in directions of and transverse to a current flow, and for the p-FET device, the at least one overhang is arranged transverse to the current flow to prevent performance degradation from compressive stresses.
REFERENCES:
patent: 3602841 (1971-08-01), McGroddy
patent: 4665415 (1987-05-01), Esaki et al.
patent: 4853076 (1989-08-01), Tsaur et al.
patent: 4855245 (1989-08-01), Neppl et al.
patent: 4952524 (1990-08-01), Lee et al.
patent: 4958213 (1990-09-01), Eklund et al.
patent: 5006913 (1991-04-01), Sugahara et al.
patent: 5060030 (1991-10-01), Hoke
patent: 5081513 (1992-01-01), Jackson et al.
patent: 5108843 (1992-04-01), Ohtaka et al.
patent: 5134085 (1992-07-01), Gilgen et al.
patent: 5310446 (1994-05-01), Konishi et al.
patent: 5354695 (1994-10-01), Leedy
patent: 5371399 (1994-12-01), Burroughes et al.
patent: 5391510 (1995-02-01), Hsu et al.
patent: 5459346 (1995-10-01), Asakawa et al.
patent: 5471948 (1995-12-01), Burroughes et al.
patent: 5557122 (1996-09-01), Shrivastava et al.
patent: 5561302 (1996-10-01), Candelaria
patent: 5565697 (1996-10-01), Asakawa et al.
patent: 5571741 (1996-11-01), Leedy
patent: 5592007 (1997-01-01), Leedy
patent: 5592018 (1997-01-01), Leedy
patent: 5670798 (1997-09-01), Schetzina
patent: 5679965 (1997-10-01), Schetzina
patent: 5683934 (1997-11-01), Candelaria
patent: 5834358 (1998-11-01), Pan et al.
patent: 5840593 (1998-11-01), Leedy
patent: 5861651 (1999-01-01), Brasen et al.
patent: 5880040 (1999-03-01), Sun et al.
patent: 5940716 (1999-08-01), Jin et al.
patent: 5940736 (1999-08-01), Brady et al.
patent: 5946559 (1999-08-01), Leedy
patent: 5953621 (1999-09-01), Gonzalez et al.
patent: 5960297 (1999-09-01), Saki
patent: 5963819 (1999-10-01), Lan
patent: 5976948 (1999-11-01), Werner et al.
patent: 5981356 (1999-11-01), Hsueh et al.
patent: 5989978 (1999-11-01), Peidous
patent: 6001707 (1999-12-01), Lin et al.
patent: 6008126 (1999-12-01), Leedy
patent: 6020622 (2000-02-01), Tsuda et al.
patent: 6022781 (2000-02-01), Noble et al.
patent: 6025280 (2000-02-01), Brady et al.
patent: 6046464 (2000-04-01), Schetzina
patent: 6066545 (2000-05-01), Doshi et al.
patent: 6080637 (2000-06-01), Huang et al.
patent: 6090684 (2000-07-01), Ishitsuka et al.
patent: 6093621 (2000-07-01), Tseng
patent: 6097076 (2000-08-01), Gonzalez et al.
patent: 6107143 (2000-08-01), Park et al.
patent: 6114741 (2000-09-01), Joyner et al.
patent: 6117722 (2000-09-01), Wuu et al.
patent: 6133071 (2000-10-01), Nagai
patent: 6143623 (2000-11-01), Tsuda et al.
patent: 6153478 (2000-11-01), Lin et al.
patent: 6165383 (2000-12-01), Chou
patent: 6180491 (2001-01-01), Joyner et al.
patent: 6221735 (2001-04-01), Manley et al.
patent: 6228694 (2001-05-01), Doyle et al.
patent: 6246095 (2001-06-01), Brady et al.
patent: 6255169 (2001-07-01), Li et al.
patent: 6261964 (2001-07-01), Wu et al.
patent: 6265317 (2001-07-01), Chiu et al.
patent: 6271143 (2001-08-01), Mendicino
patent: 6271147 (2001-08-01), Tseng
patent: 6274444 (2001-08-01), Wang
patent: 6281532 (2001-08-01), Doyle et al.
patent: 6284623 (2001-09-01), Zhang et al.
patent: 6284626 (2001-09-01), Kim
patent: 6316815 (2001-11-01), Tseng
patent: 6319794 (2001-11-01), Akatsu et al.
patent: 6361885 (2002-03-01), Chou
patent: 6362082 (2002-03-01), Doyle et al.
patent: 6368931 (2002-04-01), Kuhn et al.
patent: 6368973 (2002-04-01), Tseng
patent: 6403486 (2002-06-01), Lou
patent: 6403975 (2002-06-01), Brunner et al.
patent: 6406973 (2002-06-01), Lee
patent: 6417072 (2002-07-01), Coronel et al.
patent: 6461936 (2002-10-01), von Ehrenwall
patent: 6476462 (2002-11-01), Shimizu et al.
patent: 6483171 (2002-11-01), Forbes et al.
patent: 6493497 (2002-12-01), Ramdani et al.
patent: 6498358 (2002-12-01), Lach et al.
patent: 6501048 (2002-12-01), Strom
patent: 6501121 (2002-12-01), Yu et al.
patent: 6506652 (2003-01-01), Jan et al.
patent: 6509618 (2003-01-01), Jan et al.
patent: 6521964 (2003-02-01), Jan et al.
patent: 6531369 (2003-03-01), Ozkan et al.
patent: 6531740 (2003-03-01), Bosco et al.
patent: 6566225 (2003-05-01), Lai et al.
patent: 6583060 (2003-06-01), Trivedi
patent: 6621392 (2003-09-01), Volant et al.
patent: 6635506 (2003-10-01), Volant et al.
patent: 6717216 (2004-04-01), Doris et al.
patent: 6825529 (2004-11-01), Chidambarrao et al.
patent: 6831292 (2004-12-01), Currie et al.
patent: 6972478 (2005-12-01), Waite et al.
patent: 6974981 (2005-12-01), Chidambarrao et al.
patent: 6977194 (2005-12-01), Belyansky et al.
patent: 7015082 (2006-03-01), Doris et al.
patent: 2001/0009784 (2001-07-01), Ma et al.
patent: 2001/0014511 (2001-08-01), Pan
patent: 2002/0063292 (2002-05-01), Armstrong et al.
patent: 2002/0074598 (2002-06-01), Doyle et al.
patent: 2002/0086472 (2002-07-01), Roberds et al.
patent: 2002/0086497 (2002-07-01), Kwok
patent: 2002/0090791 (2002-07-01), Doyle et al.
patent: 2003/0032261 (2003-02-01), Yeh et al.
patent: 2003/0040158 (2003-02-01), Saitoh
patent: 2003/0057184 (2003-03-01), Yu et al.
patent: 2003/0067035 (2003-04-01), Tews et al.
patent: 2003/0127697 (2003-07-01), Ohta et al.
patent: 2003/0162400 (2003-08-01), Chen et al.
patent: 2003/0181014 (2003-09-01), Ohta et al.
patent: 2004/0238914 (2004-12-01), Deshpande et al.
patent: 2004/0262784 (2004-12-01), Doris et al.
patent: 2005/0040460 (2005-02-01), Chidambarrao et al.
patent: 2005/0082634 (2005-04-01), Doris et al.
patent: 2005/0093030 (2005-05-01), Doris et al.
patent: 2005/0098829 (2005-05-01), Doris et al.
patent: 2005/0106799 (2005-05-01), Doris et al.
patent: 2005/0145954 (2005-07-01), Zhu et al.
patent: 2005/0148146 (2005-07-01), Doris et al.
patent: 2005/0194699 (2005-09-01), Belyansky et al.
patent: 2005/0236668 (2005-10-01), Zhu et al.
patent: 2005/0245017 (2005-11-01), Belyansky et al.
patent: 2005/0280051 (2005-12-01), Chidambarrao et al.
patent: 2005/0282325 (2005-12-01), Belyansky et al.
patent: 2006/0027868 (2006-02-01), Doris et al.
patent: 2006/0057787 (2006-03-01), Doris et al.
patent: 2006/0060925 (2006-03-01), Doris et al.
patent: 1367526 (2002-09-01), None
patent: 57-80733 (1982-05-01), None
patent: 64-76755 (1989-03-01), None
patent: 2000-269466 (2000-09-01), None
patent: 10-0213196 (1997-10-01), None
Kern Rim, et al., “Transc onductance Enhancement in Deep Submicron Strained-Sin-MOSFETs”, International Electron Devices Meeting, 26, 8, 1, IEEE, Sep. 1998.
Kern Rim, et al., “Ch aracteristics and Device Design of Sub-100 nm Strained Si N- and PMOSFETs”, 2002 Symposium on VLSI Technology Digest of Technical Papers, IEEE, pp. 98-99.
Gregory Scott, et al., “NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress”, International Electron Devices Meeting, 34.4.1, IEEE, Sep. 1999.
F. Ootsuka, et al., “A Hig hly Dense, High-Performance 130nm node CMOS Technology for Large Scale System-on-a-Chip Application”, International Electron Devices Meeting, 23.5.1, IEEE, Apr. 2000.
Shinya Ito, et al., “Mecha nical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design”, International Electron Devices Meeting, 10.7.1, IEEE, Apr. 2000.
A. Shimizu, et al., “Local M echanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement”, International Electron Devices Meeting, IEEE, Mar. 2001.
K. Ota, et al. “Novel Locall y Strained Channel Technique for high Performance 55nm CMOS”. International Electron Devices Meeting, 2.2.1, IEEE, Feb. 2002.
G. Zhang, et al., &#
Doris Bruce B
Gluschenkov Oleg G
Abate Joseph P.
Garber Charles D
International Business Machines - Corporation
Isaac Stanetta D
Roberts Mlotkowski Safran & Cole P.C.
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